mirror of https://github.com/m-labs/artiq.git
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
#include <generated/csr.h>
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#include <stdio.h>
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#include "rtio.h"
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#include "dds.h"
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#define DURATION_WRITE 5
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#define DURATION_PROGRAM (8*DURATION_WRITE)
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#define DDS_WRITE(addr, data) do { \
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rtio_o_address_write(addr); \
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rtio_o_data_write(data); \
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rtio_o_timestamp_write(now); \
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rtio_write_and_process_status(now, RTIO_DDS_CHANNEL); \
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now += DURATION_WRITE; \
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} while(0)
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void dds_init(long long int timestamp, int channel)
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{
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long long int now;
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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now = timestamp - 7*DURATION_WRITE;
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(DDS_GPIO, channel | (1 << 7));
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(0x00, 0x78);
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DDS_WRITE(0x01, 0x00);
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DDS_WRITE(0x02, 0x00);
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DDS_WRITE(0x03, 0x00);
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}
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static void dds_set_one(long long int now, long long int timestamp, int channel,
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unsigned int ftw, unsigned int pow, int phase_mode)
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{
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DDS_WRITE(DDS_GPIO, channel);
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if(phase_mode == PHASE_MODE_CONTINUOUS)
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/* Do not clear phase accumulator on FUD */
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DDS_WRITE(0x02, 0x00);
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else
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/* Clear phase accumulator on FUD */
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DDS_WRITE(0x02, 0x40);
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DDS_WRITE(DDS_FTW0, ftw & 0xff);
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DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
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DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
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DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
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if(phase_mode == PHASE_MODE_TRACKING)
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/* We assume that the RTIO clock is DDS SYNCLK */
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pow += (timestamp >> RTIO_FINE_TS_WIDTH)*ftw >> 18;
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DDS_WRITE(DDS_POW0, pow & 0xff);
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DDS_WRITE(DDS_POW1, (pow >> 8) & 0x3f);
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}
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void dds_set(long long int timestamp, int channel,
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unsigned int ftw, unsigned int pow, int phase_mode)
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{
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long long int now;
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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dds_set_one(timestamp - DURATION_PROGRAM, timestamp, channel, ftw, pow, phase_mode);
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now = timestamp;
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DDS_WRITE(DDS_FUD, 0);
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}
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