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artiq/soc/targets
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Robert Jordens 9dfbf07743 pipistrello: use 4x serdes for rtio ttl 
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
2015-07-28 12:54:27 -06:00
..
artiq_kc705.py kc705: generate 10MHz clock on GPIO SMA 2015-07-28 18:56:47 +08:00
artiq_pipistrello.py pipistrello: use 4x serdes for rtio ttl 2015-07-28 12:54:27 -06:00