mirror of https://github.com/m-labs/artiq.git
62 lines
2.1 KiB
Python
62 lines
2.1 KiB
Python
from migen import *
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from .adc_ser import ADC, ADCParams
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from .iir import IIR, IIRWidths
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from .dds_ser import DDS, DDSParams
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class Servo(Module):
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def __init__(self, adc_pads, dds_pads, adc_p, iir_p, dds_p):
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self.submodules.adc = ADC(adc_pads, adc_p)
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self.submodules.iir = IIR(iir_p)
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self.submodules.dds = DDS(dds_pads, dds_p)
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# adc channels are reversed on Sampler
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for i, j, k, l in zip(reversed(self.adc.data), self.iir.adc,
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self.iir.dds, self.dds.profile):
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self.comb += j.eq(i), l.eq(k)
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t_adc = (adc_p.t_cnvh + adc_p.t_conv + adc_p.t_rtt +
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adc_p.channels*adc_p.width//adc_p.lanes) + 1
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t_iir = ((1 + 4 + 1) << iir_p.channel) + 1
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t_dds = (dds_p.width*2 + 1)*dds_p.clk + 1
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t_cycle = max(t_adc, t_iir, t_dds)
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assert t_iir + (2 << iir_p.channel) < t_cycle, "need shifting time"
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self.start = Signal()
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t_restart = t_cycle - t_adc + 1
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assert t_restart > 1
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cnt = Signal(max=t_restart)
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cnt_done = Signal()
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active = Signal(3)
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self.done = Signal()
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self.sync += [
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If(self.dds.done,
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active[2].eq(0)
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),
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If(self.dds.start & self.dds.done,
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active[2].eq(1),
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active[1].eq(0)
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),
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If(self.iir.start & self.iir.done,
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active[1].eq(1),
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active[0].eq(0)
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),
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If(~cnt_done & self.adc.done,
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cnt.eq(cnt - 1)
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),
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If(self.adc.start & self.adc.done,
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active[0].eq(1),
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cnt.eq(t_restart - 1)
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)
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]
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self.comb += [
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cnt_done.eq(cnt == 0),
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self.adc.start.eq(self.start & cnt_done),
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self.iir.start.eq(active[0] & self.adc.done),
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self.dds.start.eq(active[1] &
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(self.iir.shifting | self.iir.done)),
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self.done.eq(self.dds.done),
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]
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