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294 lines
8.8 KiB
Python
294 lines
8.8 KiB
Python
"""RTIO driver for Mirny (4 channel GHz PLLs)
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"""
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from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable
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from artiq.language.units import us
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from numpy import int32
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from artiq.coredevice.core import Core
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from artiq.coredevice.spi2 import *
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# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189
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@nac3
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class ValueError(Exception):
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pass
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SPI_CONFIG = (
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0 * SPI_OFFLINE
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| 0 * SPI_END
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| 0 * SPI_INPUT
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| 1 * SPI_CS_POLARITY
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| 0 * SPI_CLK_POLARITY
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| 0 * SPI_CLK_PHASE
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| 0 * SPI_LSB_FIRST
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| 0 * SPI_HALF_DUPLEX
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)
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# SPI clock write and read dividers
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SPIT_WR = 4
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SPIT_RD = 16
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SPI_CS = 1
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WE = 1 << 24
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# supported CPLD code version
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PROTO_REV_MATCH = 0x0
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# almazny-specific data
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ALMAZNY_REG_BASE = 0x0C
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ALMAZNY_OE_SHIFT = 12
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# higher SPI write divider to match almazny shift register timing
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# min SER time before SRCLK rise = 125ns
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# -> div=32 gives 125ns for data before clock rise
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# works at faster dividers too but could be less reliable
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ALMAZNY_SPIT_WR = 32
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@nac3
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class Mirny:
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"""
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Mirny PLL-based RF generator.
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:param spi_device: SPI bus device
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:param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
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frequency in Hz
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:param clk_sel: Reference clock selection.
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Valid options are: "XO" - onboard crystal oscillator;
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"SMA" - front-panel SMA connector; "MMCX" - internal MMCX connector.
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Passing an integer writes it as ``clk_sel`` in the CPLD's register 1.
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The effect depends on the hardware revision.
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:param core_device: Core device name (default: "core")
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"""
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core: KernelInvariant[Core]
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bus: KernelInvariant[SPIMaster]
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refclk: KernelInvariant[float]
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clk_sel_hw_rev: Kernel[list[int32]]
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hw_rev: Kernel[int32]
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clk_sel: Kernel[int32]
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def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel="XO", core_device="core"):
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self.core = dmgr.get(core_device)
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self.bus = dmgr.get(spi_device)
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# reference clock frequency
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self.refclk = refclk
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if not (10 <= self.refclk / 1e6 <= 600):
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raise ValueError("Invalid refclk")
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# reference clock selection
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try:
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self.clk_sel_hw_rev = {
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# clk source: [reserved, reserved, v1.1, v1.0]
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"xo": [-1, -1, 0, 0],
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"mmcx": [-1, -1, 3, 2],
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"sma": [-1, -1, 2, 3],
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}[clk_sel.lower()]
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except AttributeError: # not a string, fallback to int
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if clk_sel & 0x3 != clk_sel:
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raise ValueError("Invalid clk_sel") from None
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self.clk_sel_hw_rev = [clk_sel] * 4
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except KeyError:
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raise ValueError("Invalid clk_sel") from None
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self.clk_sel = -1
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# board hardware revision
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self.hw_rev = 0 # v1.0: 3, v1.1: 2
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# TODO: support clk_div on v1.0 boards
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@kernel
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def read_reg(self, addr: int32) -> int32:
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"""Read a register"""
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self.bus.set_config_mu(
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SPI_CONFIG | SPI_INPUT | SPI_END, 24, SPIT_RD, SPI_CS
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)
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self.bus.write((addr << 25))
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return self.bus.read() & 0xFFFF
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@kernel
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def write_reg(self, addr: int32, data: int32):
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"""Write a register"""
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 24, SPIT_WR, SPI_CS)
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self.bus.write((addr << 25) | WE | ((data & 0xFFFF) << 8))
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@kernel
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def init(self, blind: bool = False):
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"""
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Initialize and detect Mirny.
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Select the clock source based the board's hardware revision.
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Raise ValueError if the board's hardware revision is not supported.
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:param blind: Verify presence and protocol compatibility. Raise ValueError on failure.
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"""
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reg0 = self.read_reg(0)
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self.hw_rev = reg0 & 0x3
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if not blind:
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if (reg0 >> 2) & 0x3 != PROTO_REV_MATCH:
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raise ValueError("Mirny PROTO_REV mismatch")
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self.core.delay(100. * us) # slack
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# select clock source
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self.clk_sel = self.clk_sel_hw_rev[self.hw_rev]
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if self.clk_sel < 0:
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raise ValueError("Hardware revision not supported")
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self.write_reg(1, (self.clk_sel << 4))
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self.core.delay(1000. * us)
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@portable
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def att_to_mu(self, att: float) -> int32:
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"""Convert an attenuation setting in dB to machine units.
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:param att: Attenuation setting in dB.
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:return: Digital attenuation setting.
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"""
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code = int32(255) - int32(round(att * 8.))
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if code < 0 or code > 255:
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raise ValueError("Invalid Mirny attenuation!")
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return code
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@kernel
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def set_att_mu(self, channel: int32, att: int32):
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"""Set digital step attenuator in machine units.
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:param att: Attenuation setting, 8 bit digital.
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"""
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 16, SPIT_WR, SPI_CS)
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self.bus.write(((channel | 8) << 25) | (att << 16))
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@kernel
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def set_att(self, channel: int32, att: float):
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"""Set digital step attenuator in SI units.
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This method will write the attenuator settings of the selected channel.
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.. seealso:: :meth:`set_att_mu`
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:param channel: Attenuator channel (0-3).
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:param att: Attenuation setting in dB. Higher value is more
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attenuation. Minimum attenuation is 0*dB, maximum attenuation is
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31.5*dB.
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"""
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self.set_att_mu(channel, self.att_to_mu(att))
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@kernel
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def write_ext(self, addr: int32, length: int32, data: int32, ext_div: int32 = SPIT_WR):
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"""Perform SPI write to a prefixed address"""
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self.bus.set_config_mu(SPI_CONFIG, 8, SPIT_WR, SPI_CS)
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self.bus.write(addr << 25)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, length, ext_div, SPI_CS)
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if length < 32:
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data <<= 32 - length
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self.bus.write(data)
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class Almazny:
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"""
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Almazny (High frequency mezzanine board for Mirny)
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:param host_mirny - Mirny device Almazny is connected to
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"""
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def __init__(self, dmgr, host_mirny):
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self.mirny_cpld = dmgr.get(host_mirny)
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self.att_mu = [0x3f] * 4
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self.channel_sw = [0] * 4
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self.output_enable = False
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@kernel
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def init(self):
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self.output_toggle(self.output_enable)
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@kernel
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def att_to_mu(self, att):
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"""
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Convert an attenuator setting in dB to machine units.
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:param att: attenuator setting in dB [0-31.5]
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:return: attenuator setting in machine units
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"""
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mu = round(att * 2.0)
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if mu > 63 or mu < 0:
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raise ValueError("Invalid Almazny attenuator settings!")
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return mu
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@kernel
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def mu_to_att(self, att_mu):
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"""
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Convert a digital attenuator setting to dB.
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:param att_mu: attenuator setting in machine units
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:return: attenuator setting in dB
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"""
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return att_mu / 2
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@kernel
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def set_att(self, channel, att, rf_switch=True):
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"""
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Sets attenuators on chosen shift register (channel).
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:param channel - index of the register [0-3]
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:param att_mu - attenuation setting in dBm [0-31.5]
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:param rf_switch - rf switch (bool)
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"""
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self.set_att_mu(channel, self.att_to_mu(att), rf_switch)
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@kernel
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def set_att_mu(self, channel, att_mu, rf_switch=True):
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"""
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Sets attenuators on chosen shift register (channel).
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:param channel - index of the register [0-3]
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:param att_mu - attenuation setting in machine units [0-63]
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:param rf_switch - rf switch (bool)
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"""
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self.channel_sw[channel] = 1 if rf_switch else 0
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self.att_mu[channel] = att_mu
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self._update_register(channel)
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@kernel
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def output_toggle(self, oe):
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"""
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Toggles output on all shift registers on or off.
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:param oe - toggle output enable (bool)
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"""
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self.output_enable = oe
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cfg_reg = self.mirny_cpld.read_reg(1)
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en = 1 if self.output_enable else 0
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delay(100 * us)
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new_reg = (en << ALMAZNY_OE_SHIFT) | (cfg_reg & 0x3FF)
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self.mirny_cpld.write_reg(1, new_reg)
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delay(100 * us)
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@kernel
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def _flip_mu_bits(self, mu):
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# in this form MSB is actually 0.5dB attenuator
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# unnatural for users, so we flip the six bits
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return (((mu & 0x01) << 5)
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| ((mu & 0x02) << 3)
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| ((mu & 0x04) << 1)
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| ((mu & 0x08) >> 1)
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| ((mu & 0x10) >> 3)
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| ((mu & 0x20) >> 5))
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@kernel
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def _update_register(self, ch):
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self.mirny_cpld.write_ext(
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ALMAZNY_REG_BASE + ch,
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8,
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self._flip_mu_bits(self.att_mu[ch]) | (self.channel_sw[ch] << 6),
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ALMAZNY_SPIT_WR
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)
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delay(100 * us)
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@kernel
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def _update_all_registers(self):
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for i in range(4):
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self._update_register(i) |