mirror of
https://github.com/m-labs/artiq.git
synced 2025-01-09 10:33:35 +08:00
564 lines
20 KiB
Rust
564 lines
20 KiB
Rust
#![feature(never_type, panic_implementation, panic_info_message, const_slice_len, try_from)]
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#![no_std]
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#[macro_use]
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extern crate log;
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#[macro_use]
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extern crate board_misoc;
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extern crate board_artiq;
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use core::convert::TryFrom;
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use board_misoc::{csr, irq, ident, clock, uart_logger};
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use board_artiq::{i2c, spi, si5324, drtioaux};
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#[cfg(has_serwb_phy_amc)]
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use board_artiq::serwb;
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use board_artiq::drtio_routing;
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#[cfg(has_hmc830_7043)]
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use board_artiq::hmc830_7043;
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mod repeater;
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fn drtiosat_reset(reset: bool) {
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unsafe {
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csr::drtiosat::reset_write(if reset { 1 } else { 0 });
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}
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}
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fn drtiosat_reset_phy(reset: bool) {
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unsafe {
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csr::drtiosat::reset_phy_write(if reset { 1 } else { 0 });
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}
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}
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fn drtiosat_link_rx_up() -> bool {
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unsafe {
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csr::drtiosat::rx_up_read() == 1
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}
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}
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fn drtiosat_tsc_loaded() -> bool {
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unsafe {
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let tsc_loaded = csr::drtiosat::tsc_loaded_read() == 1;
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if tsc_loaded {
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csr::drtiosat::tsc_loaded_write(1);
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}
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tsc_loaded
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}
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}
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#[cfg(has_drtio_routing)]
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macro_rules! forward {
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($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr) => {{
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let hop = $routing_table.0[$destination as usize][$rank as usize];
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if hop != 0 {
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let repno = (hop - 1) as usize;
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if repno < $repeaters.len() {
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return $repeaters[repno].aux_forward($packet);
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} else {
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return Err(drtioaux::Error::RoutingError);
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}
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}
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}}
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}
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#[cfg(not(has_drtio_routing))]
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macro_rules! forward {
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($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr) => {}
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}
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fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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_routing_table: &mut drtio_routing::RoutingTable, _rank: &mut u8,
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packet: drtioaux::Packet) -> Result<(), drtioaux::Error<!>> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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match packet {
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drtioaux::Packet::EchoRequest =>
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drtioaux::send(0, &drtioaux::Packet::EchoReply),
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drtioaux::Packet::ResetRequest => {
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info!("resetting RTIO");
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drtiosat_reset(true);
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clock::spin_us(100);
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drtiosat_reset(false);
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for rep in _repeaters.iter() {
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if let Err(e) = rep.rtio_reset() {
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error!("failed to issue RTIO reset ({})", e);
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}
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}
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drtioaux::send(0, &drtioaux::Packet::ResetAck)
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},
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drtioaux::Packet::DestinationStatusRequest { destination: _destination } => {
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#[cfg(has_drtio_routing)]
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let hop = _routing_table.0[_destination as usize][*_rank as usize];
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#[cfg(not(has_drtio_routing))]
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let hop = 0;
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if hop == 0 {
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let errors;
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unsafe {
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errors = csr::drtiosat::rtio_error_read();
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}
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if errors & 1 != 0 {
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let channel;
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unsafe {
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channel = csr::drtiosat::sequence_error_channel_read();
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csr::drtiosat::rtio_error_write(1);
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}
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drtioaux::send(0,
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&drtioaux::Packet::DestinationSequenceErrorReply { channel })?;
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} else if errors & 2 != 0 {
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let channel;
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unsafe {
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channel = csr::drtiosat::collision_channel_read();
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csr::drtiosat::rtio_error_write(2);
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}
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drtioaux::send(0,
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&drtioaux::Packet::DestinationCollisionReply { channel })?;
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} else if errors & 4 != 0 {
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let channel;
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unsafe {
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channel = csr::drtiosat::busy_channel_read();
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csr::drtiosat::rtio_error_write(4);
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}
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drtioaux::send(0,
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&drtioaux::Packet::DestinationBusyReply { channel })?;
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}
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else {
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drtioaux::send(0, &drtioaux::Packet::DestinationOkReply)?;
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}
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}
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#[cfg(has_drtio_routing)]
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{
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if hop != 0 {
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let hop = hop as usize;
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if hop <= csr::DRTIOREP.len() {
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let repno = hop - 1;
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match _repeaters[repno].aux_forward(&drtioaux::Packet::DestinationStatusRequest {
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destination: _destination
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}) {
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Ok(()) => (),
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Err(drtioaux::Error::LinkDown) => drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?,
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Err(e) => {
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drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
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error!("aux error when handling destination status request: {}", e);
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},
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}
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} else {
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drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
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}
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}
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}
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Ok(())
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}
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#[cfg(has_drtio_routing)]
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drtioaux::Packet::RoutingSetPath { destination, hops } => {
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_routing_table.0[destination as usize] = hops;
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for rep in _repeaters.iter() {
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if let Err(e) = rep.set_path(destination, &hops) {
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error!("failed to set path ({})", e);
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}
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}
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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#[cfg(has_drtio_routing)]
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drtioaux::Packet::RoutingSetRank { rank } => {
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*_rank = rank;
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drtio_routing::interconnect_enable_all(_routing_table, rank);
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let rep_rank = rank + 1;
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for rep in _repeaters.iter() {
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if let Err(e) = rep.set_rank(rep_rank) {
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error!("failed to set rank ({})", e);
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}
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}
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info!("rank: {}", rank);
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info!("routing table: {}", _routing_table);
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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#[cfg(not(has_drtio_routing))]
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drtioaux::Packet::RoutingSetPath { destination: _, hops: _ } => {
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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#[cfg(not(has_drtio_routing))]
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drtioaux::Packet::RoutingSetRank { rank: _ } => {
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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drtioaux::Packet::MonitorRequest { destination: _destination, channel, probe } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let value;
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#[cfg(has_rtio_moninj)]
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unsafe {
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csr::rtio_moninj::mon_chan_sel_write(channel as _);
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csr::rtio_moninj::mon_probe_sel_write(probe);
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csr::rtio_moninj::mon_value_update_write(1);
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value = csr::rtio_moninj::mon_value_read();
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}
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#[cfg(not(has_rtio_moninj))]
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{
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value = 0;
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}
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let reply = drtioaux::Packet::MonitorReply { value: value as u32 };
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drtioaux::send(0, &reply)
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},
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drtioaux::Packet::InjectionRequest { destination: _destination, channel, overrd, value } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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#[cfg(has_rtio_moninj)]
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unsafe {
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csr::rtio_moninj::inj_chan_sel_write(channel as _);
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csr::rtio_moninj::inj_override_sel_write(overrd);
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csr::rtio_moninj::inj_value_write(value);
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}
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Ok(())
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},
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drtioaux::Packet::InjectionStatusRequest { destination: _destination, channel, overrd } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let value;
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#[cfg(has_rtio_moninj)]
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unsafe {
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csr::rtio_moninj::inj_chan_sel_write(channel as _);
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csr::rtio_moninj::inj_override_sel_write(overrd);
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value = csr::rtio_moninj::inj_value_read();
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}
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#[cfg(not(has_rtio_moninj))]
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{
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value = 0;
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}
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drtioaux::send(0, &drtioaux::Packet::InjectionStatusReply { value: value })
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},
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drtioaux::Packet::I2cStartRequest { destination: _destination, busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let succeeded = i2c::start(busno).is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cRestartRequest { destination: _destination, busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let succeeded = i2c::restart(busno).is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cStopRequest { destination: _destination, busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let succeeded = i2c::stop(busno).is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cWriteRequest { destination: _destination, busno, data } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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match i2c::write(busno, data) {
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Ok(ack) => drtioaux::send(0,
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&drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
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Err(_) => drtioaux::send(0,
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&drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false })
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}
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}
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drtioaux::Packet::I2cReadRequest { destination: _destination, busno, ack } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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match i2c::read(busno, ack) {
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Ok(data) => drtioaux::send(0,
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&drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
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Err(_) => drtioaux::send(0,
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&drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
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}
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}
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drtioaux::Packet::SpiSetConfigRequest { destination: _destination, busno, flags, length, div, cs } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::SpiBasicReply { succeeded: succeeded })
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},
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drtioaux::Packet::SpiWriteRequest { destination: _destination, busno, data } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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let succeeded = spi::write(busno, data).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::SpiBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::SpiReadRequest { destination: _destination, busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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match spi::read(busno) {
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Ok(data) => drtioaux::send(0,
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&drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
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Err(_) => drtioaux::send(0,
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&drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
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}
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}
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_ => {
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warn!("received unexpected aux packet");
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Ok(())
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}
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}
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}
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fn process_aux_packets(repeaters: &mut [repeater::Repeater],
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routing_table: &mut drtio_routing::RoutingTable, rank: &mut u8) {
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let result =
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drtioaux::recv(0).and_then(|packet| {
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if let Some(packet) = packet {
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process_aux_packet(repeaters, routing_table, rank, packet)
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} else {
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Ok(())
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}
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});
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match result {
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Ok(()) => (),
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Err(e) => warn!("aux packet error ({})", e)
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}
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}
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fn drtiosat_process_errors() {
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let errors;
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unsafe {
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errors = csr::drtiosat::protocol_error_read();
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}
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if errors & 1 != 0 {
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error!("received packet of an unknown type");
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}
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if errors & 2 != 0 {
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error!("received truncated packet");
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}
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if errors & 4 != 0 {
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let destination;
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unsafe {
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destination = csr::drtiosat::buffer_space_timeout_dest_read();
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}
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error!("timeout attempting to get buffer space from CRI, destination=0x{:02x}", destination)
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}
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if errors & 8 != 0 {
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let channel;
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let timestamp_event;
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let timestamp_counter;
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unsafe {
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channel = csr::drtiosat::underflow_channel_read();
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timestamp_event = csr::drtiosat::underflow_timestamp_event_read() as i64;
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timestamp_counter = csr::drtiosat::underflow_timestamp_counter_read() as i64;
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}
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error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
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channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
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}
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if errors & 16 != 0 {
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error!("write overflow");
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}
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unsafe {
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csr::drtiosat::protocol_error_write(errors);
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}
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}
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#[cfg(has_rtio_crg)]
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fn init_rtio_crg() {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
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if !locked {
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error!("RTIO clock failed");
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}
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}
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#[cfg(not(has_rtio_crg))]
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fn init_rtio_crg() { }
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fn hardware_tick(ts: &mut u64) {
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let now = clock::get_ms();
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if now > *ts {
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#[cfg(has_grabber)]
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board_artiq::grabber::tick();
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*ts = now + 200;
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}
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}
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#[cfg(rtio_frequency = "150.0")]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 6,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 270,
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n31 : 75,
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n32 : 75,
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bwsel : 4,
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crystal_ref: true
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};
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#[cfg(rtio_frequency = "125.0")]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: true
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};
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#[no_mangle]
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pub extern fn main() -> i32 {
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clock::init();
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uart_logger::ConsoleLogger::register();
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info!("ARTIQ satellite manager starting...");
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info!("software ident {}", csr::CONFIG_IDENTIFIER_STR);
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info!("gateware ident {}", ident::read(&mut [0; 64]));
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#[cfg(has_slave_fpga_cfg)]
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board_artiq::slave_fpga::load().expect("cannot load RTM FPGA gateware");
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#[cfg(has_serwb_phy_amc)]
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serwb::wait_init();
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i2c::init();
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si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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#[cfg(has_hmc830_7043)]
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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clock::spin_us(1500); // wait for CPLL/QPLL lock
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init_rtio_crg();
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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#[cfg(has_drtio_routing)]
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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#[cfg(not(has_drtio_routing))]
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let mut repeaters = [repeater::Repeater::default(); 0];
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for i in 0..repeaters.len() {
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repeaters[i] = repeater::Repeater::new(i as u8);
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}
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let mut routing_table = drtio_routing::RoutingTable::default_empty();
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let mut rank = 1;
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let mut hardware_tick_ts = 0;
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loop {
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while !drtiosat_link_rx_up() {
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drtiosat_process_errors();
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for mut rep in repeaters.iter_mut() {
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rep.service(&routing_table, rank);
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}
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hardware_tick(&mut hardware_tick_ts);
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}
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info!("uplink is up, switching to recovered clock");
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si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
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si5324::siphaser::calibrate_skew().expect("failed to calibrate skew");
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#[cfg(has_ad9154)]
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{
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/*
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* One side of the JESD204 elastic buffer is clocked by the Si5324, the other
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* by the RTM.
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* The elastic buffer can operate only when those two clocks are derived from
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* the same oscillator.
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* This is the case when either of those conditions is true:
|
|
* (1) The DRTIO master and the RTM are clocked directly from a common external
|
|
* source, *and* the Si5324 has locked to the recovered clock.
|
|
* This clocking scheme provides less noise and phase drift at the DACs.
|
|
* (2) The RTM clock is connected to the Si5324 output.
|
|
* To handle those cases, we simply keep the JESD204 core in reset unless the
|
|
* Si5324 is locked to the recovered clock.
|
|
*/
|
|
board_artiq::ad9154::jesd_reset(false);
|
|
board_artiq::ad9154::init();
|
|
}
|
|
|
|
drtioaux::reset(0);
|
|
drtiosat_reset(false);
|
|
drtiosat_reset_phy(false);
|
|
|
|
while drtiosat_link_rx_up() {
|
|
drtiosat_process_errors();
|
|
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank);
|
|
for mut rep in repeaters.iter_mut() {
|
|
rep.service(&routing_table, rank);
|
|
}
|
|
hardware_tick(&mut hardware_tick_ts);
|
|
if drtiosat_tsc_loaded() {
|
|
info!("TSC loaded from uplink");
|
|
#[cfg(has_ad9154)]
|
|
{
|
|
if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
|
|
error!("failed to align SYSREF at FPGA: {}", e);
|
|
}
|
|
if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
|
|
error!("failed to align SYSREF at DAC: {}", e);
|
|
}
|
|
}
|
|
for rep in repeaters.iter() {
|
|
if let Err(e) = rep.sync_tsc() {
|
|
error!("failed to sync TSC ({})", e);
|
|
}
|
|
}
|
|
if let Err(e) = drtioaux::send(0, &drtioaux::Packet::TSCAck) {
|
|
error!("aux packet error: {}", e);
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(has_ad9154)]
|
|
board_artiq::ad9154::jesd_reset(true);
|
|
|
|
drtiosat_reset_phy(true);
|
|
drtiosat_reset(true);
|
|
drtiosat_tsc_loaded();
|
|
info!("uplink is down, switching to local crystal clock");
|
|
si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
|
|
}
|
|
}
|
|
|
|
#[no_mangle]
|
|
pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
|
|
let vect = irq::Exception::try_from(vect).expect("unknown exception");
|
|
|
|
fn hexdump(addr: u32) {
|
|
let addr = (addr - addr % 4) as *const u32;
|
|
let mut ptr = addr;
|
|
println!("@ {:08p}", ptr);
|
|
for _ in 0..4 {
|
|
print!("+{:04x}: ", ptr as usize - addr as usize);
|
|
print!("{:08x} ", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
print!("{:08x} ", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
print!("{:08x} ", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
print!("{:08x}\n", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
}
|
|
}
|
|
|
|
hexdump(pc);
|
|
hexdump(ea);
|
|
panic!("exception {:?} at PC 0x{:x}, EA 0x{:x}", vect, pc, ea)
|
|
}
|
|
|
|
#[no_mangle]
|
|
pub extern fn abort() {
|
|
println!("aborted");
|
|
loop {}
|
|
}
|
|
|
|
#[no_mangle] // https://github.com/rust-lang/rust/issues/{38281,51647}
|
|
#[panic_implementation]
|
|
pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
|
|
if let Some(location) = info.location() {
|
|
print!("panic at {}:{}:{}", location.file(), location.line(), location.column());
|
|
} else {
|
|
print!("panic at unknown location");
|
|
}
|
|
if let Some(message) = info.message() {
|
|
println!(": {}", message);
|
|
} else {
|
|
println!("");
|
|
}
|
|
loop {}
|
|
}
|