mirror of https://github.com/m-labs/artiq.git
102 lines
3.6 KiB
Python
102 lines
3.6 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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# This code assumes 125/62.5MHz reference clock and 125MHz or 150MHz RTIO
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# frequency.
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class SiPhaser7Series(Module, AutoCSR):
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def __init__(self, si5324_clkin, si5324_clkout_fabric,
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ref_clk=None, ref_div2=False, rtio_clk_freq=150e6):
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self.switch_clocks = CSRStorage()
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus(reset=1)
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self.sample_result = CSRStatus()
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assert rtio_clk_freq in (125e6, 150e6)
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# 125MHz/62.5MHz reference clock to 125MHz/150MHz. VCO @ 750MHz.
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# Used to provide a startup clock to the transceiver through the Si,
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# we do not use the crystal reference so that the PFD (f3) frequency
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# can be high.
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mmcm_freerun_fb = Signal()
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mmcm_freerun_output = Signal()
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self.specials += \
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=16.0 if ref_div2 else 8.0,
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i_CLKIN1=ClockSignal("sys") if ref_clk is None else ref_clk,
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i_RST=ResetSignal("sys") if ref_clk is None else 0,
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p_CLKFBOUT_MULT_F=12.0 if ref_div2 else 6.0,
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p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
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p_CLKOUT0_DIVIDE_F=750e6/rtio_clk_freq,
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o_CLKOUT0=mmcm_freerun_output,
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)
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# 125MHz/150MHz to 125MHz/150MHz with controllable phase shift,
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# VCO @ 1000MHz/1200MHz.
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# Inserted between CDR and output to Si, used to correct
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# non-determinstic skew of Si5324.
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mmcm_ps_fb = Signal()
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mmcm_ps_output = Signal()
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mmcm_ps_psdone = Signal()
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self.specials += \
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio_rx0"),
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i_RST=ResetSignal("rtio_rx0"),
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i_CLKINSEL=1, # yes, 1=CLKIN1 0=CLKIN2
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p_CLKFBOUT_MULT_F=8.0,
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p_CLKOUT0_DIVIDE_F=8.0,
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p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=mmcm_ps_output,
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSINCDEC=self.phase_shift.r,
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o_PSDONE=mmcm_ps_psdone,
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)
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self.sync += [
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If(self.phase_shift.re, self.phase_shift_done.status.eq(0)),
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If(mmcm_ps_psdone, self.phase_shift_done.status.eq(1))
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]
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si5324_clkin_se = Signal()
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self.specials += [
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Instance("BUFGMUX",
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i_I0=mmcm_freerun_output,
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i_I1=mmcm_ps_output,
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i_S=self.switch_clocks.storage,
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o_O=si5324_clkin_se
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),
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Instance("OBUFDS",
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i_I=si5324_clkin_se,
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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]
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si5324_clkout_se = Signal()
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self.specials += \
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Instance("IBUFDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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i_I=si5324_clkout_fabric.p, i_IB=si5324_clkout_fabric.n,
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o_O=si5324_clkout_se),
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clkout_sample1 = Signal() # IOB register
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self.sync.rtio_rx0 += clkout_sample1.eq(si5324_clkout_se)
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self.specials += MultiReg(clkout_sample1, self.sample_result.status)
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# expose MMCM outputs - used for clock constraints
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self.mmcm_freerun_output = mmcm_freerun_output
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self.mmcm_ps_output = mmcm_ps_output
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