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artiq/artiq/master
David Nadlinger 966ed5d013 master/scheduler: Fix priority/due date precedence order when waiting to prepare
See test case – previously, the highest-priority pending run would
be used to calculate the timeout, rather than the earliest one.

This probably managed to go undetected for that long as any unrelated
changes to the pipeline (e.g. new submissions, or experiments pausing)
would also cause _get_run() to be re-evaluated.
2020-06-19 23:45:52 +01:00
..
__init__.py separate master modules 2015-01-14 12:16:49 +08:00
databases.py fix device_db alias corner case bugs. Closes #1140 2019-11-14 16:22:45 +08:00
experiments.py use sipyco (#585) 2019-11-10 15:55:17 +08:00
log.py use sipyco (#585) 2019-11-10 15:55:17 +08:00
rid_counter.py master: Factor RIDCounter out into own module, explain worker_db module [nfc] 2018-10-14 10:41:32 +08:00
scheduler.py master/scheduler: Fix priority/due date precedence order when waiting to prepare 2020-06-19 23:45:52 +01:00
worker_db.py fix device_db alias corner case bugs. Closes #1140 2019-11-14 16:22:45 +08:00
worker_impl.py master: Always write results to HDF5 once run stage is reached 2020-06-18 17:47:26 +01:00
worker.py master: Always write results to HDF5 once run stage is reached 2020-06-18 17:47:26 +01:00