mirror of https://github.com/m-labs/artiq.git
105 lines
2.7 KiB
Python
105 lines
2.7 KiB
Python
import logging
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from collections import namedtuple
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from migen import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib import io
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from .tools import DiffMixin
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logger = logging.getLogger(__name__)
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# all times in cycles
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SPIParams = namedtuple("SPIParams", [
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"channels", # number of MOSI? data lanes
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"width", # transfer width
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"clk", # CLK half cycle width (in cycles)
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])
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class SPISimple(Module, DiffMixin):
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"""Simple reduced SPI interface.
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* Multiple MOSI lines
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* Supports differential CLK/CS_N/MOSI
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* Fixed CLK timing
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* SPI MODE 0 (CPHA=0, CPOL=0)
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"""
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def __init__(self, pads, params):
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self.params = p = params
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self.data = [Signal(p.width, reset_less=True)
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for i in range(p.channels)] # data to be output, MSB first
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self.start = Signal() # start transfer
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self.done = Signal() # transfer complete, next transfer can be
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# started
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###
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assert p.clk >= 1
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cs_n = self._diff(pads, "cs_n", output=True)
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clk = self._diff(pads, "clk", output=True)
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cnt = Signal(max=max(2, p.clk), reset_less=True)
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cnt_done = Signal()
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cnt_next = Signal()
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self.comb += cnt_done.eq(cnt == 0)
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self.sync += [
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If(cnt_done,
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If(cnt_next,
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cnt.eq(p.clk - 1)
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)
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).Else(
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cnt.eq(cnt - 1)
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)
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]
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for i, d in enumerate(self.data):
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self.comb += [
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self._diff(pads, "mosi{}".format(i), output=True).eq(d[-1])
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]
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bits = Signal(max=p.width + 1, reset_less=True)
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self.submodules.fsm = fsm = CEInserter()(FSM("IDLE"))
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self.comb += [
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fsm.ce.eq(cnt_done)
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]
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fsm.act("IDLE",
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self.done.eq(1),
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cs_n.eq(1),
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If(self.start,
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cnt_next.eq(1),
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NextState("SETUP")
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)
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)
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fsm.act("SETUP",
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cnt_next.eq(1),
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If(bits == 0,
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NextState("IDLE")
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).Else(
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NextState("HOLD")
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)
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)
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fsm.act("HOLD",
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cnt_next.eq(1),
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clk.eq(1),
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NextState("SETUP")
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)
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self.sync += [
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If(fsm.ce,
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If(fsm.before_leaving("HOLD"),
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bits.eq(bits - 1),
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[d[1:].eq(d) for d in self.data]
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),
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If(fsm.ongoing("IDLE"),
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bits.eq(p.width)
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)
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)
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]
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