mirror of https://github.com/m-labs/artiq.git
678 lines
24 KiB
Python
678 lines
24 KiB
Python
from collections import namedtuple
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import logging
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from migen import *
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logger = logging.getLogger(__name__)
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# all these are number of bits!
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IIRWidths = namedtuple("IIRWidths", [
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"state", # the signed x and y states of the IIR filter
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# DSP A input, x state is one bit smaller
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# due to AD pre-adder, y has full width (25)
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"coeff", # signed IIR filter coefficients a1, b0, b1 (18)
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"accu", # IIR accumulator width (48)
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"adc", # signed ADC data (16)
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"word", # "word" size to break up DDS profile data (16)
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"asf", # unsigned amplitude scale factor for DDS (14)
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"shift", # fixed point scaling coefficient for a1, b0, b1 (log2!) (11)
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"channel", # channels (log2!) (3)
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"profile", # profiles per channel (log2!) (5)
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])
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def signed(v, w):
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"""Convert an unsigned integer ``v`` to it's signed value assuming ``w``
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bits"""
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assert 0 <= v < (1 << w)
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if v & (1 << w - 1):
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v -= 1 << w
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return v
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class DSP(Module):
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"""Thin abstraction of DSP functionality used here, commonly present,
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and inferrable in FPGAs: multiplier with pre-adder and post-accumulator
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and pipeline registers at every stage."""
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def __init__(self, w, signed_output=False):
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self.state = Signal((w.state, True))
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# NOTE:
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# If offset is non-zero, care must be taken to ensure that the
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# offset-state difference does not overflow the width of the ad factor
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# which is also w.state.
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self.offset = Signal((w.state, True))
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self.coeff = Signal((w.coeff, True))
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self.output = Signal((w.state, True))
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self.accu_clr = Signal()
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self.offset_load = Signal()
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self.clip = Signal()
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a = Signal((w.state, True), reset_less=True)
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d = Signal((w.state, True), reset_less=True)
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ad = Signal((w.state, True), reset_less=True)
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b = Signal((w.coeff, True), reset_less=True)
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m = Signal((w.accu, True), reset_less=True)
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p = Signal((w.accu, True), reset_less=True)
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self.sync += [
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a.eq(self.state),
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If(self.offset_load,
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d.eq(self.offset)
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),
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ad.eq(d - a),
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b.eq(self.coeff),
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m.eq(ad*b),
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p.eq(p + m),
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If(self.accu_clr,
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# inject symmetric rouding constant
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# p.eq(1 << (w.shift - 1))
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# but that won't infer P reg, so we just clear
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# and round down
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p.eq(0),
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)
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]
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# Bit layout (LSB-MSB): w.shift | w.state - 1 | n_sign - 1 | 1 (sign)
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n_sign = w.accu - w.state - w.shift + 1
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assert n_sign > 1
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# clipping
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if signed_output:
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self.comb += [
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self.clip.eq(p[-n_sign:] != Replicate(p[-1], n_sign)),
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self.output.eq(Mux(self.clip,
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Cat(Replicate(~p[-1], w.state - 1), p[-1]),
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p[w.shift:]))
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]
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else:
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self.comb += [
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self.clip.eq(p[-n_sign:] != 0),
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self.output.eq(Mux(self.clip,
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Replicate(~p[-1], w.state - 1),
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p[w.shift:]))
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]
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class IIR(Module):
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"""Pipelined IIR processor.
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This module implements a multi-channel IIR (infinite impulse response)
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filter processor optimized for synthesis on FPGAs.
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The module is parametrized by passing a ``IIRWidths()`` object which
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will be abbreviated W here.
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It reads 1 << W.channels input channels (typically from an ADC)
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and on each iteration processes the data on using a first-order IIR filter.
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At the end of the cycle each the output of the filter together with
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additional data (typically frequency tunning word and phase offset word
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for a DDS) are presented at the 1 << W.channels outputs of the module.
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Profile memory
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==============
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Each channel can operate using any of its 1 << W.profile profiles.
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The profile data consists of the input ADC channel index (SEL), a delay
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(DLY) for delayed activation of the IIR updates, the three IIR
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coefficients (A1, B0, B1), the input offset (OFFSET), and additional data
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(FTW0, FTW1, and POW). Profile data is stored in a dual-port block RAM that
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can be accessed externally.
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Memory Layout
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-------------
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The profile data is stored sequentially for each channel.
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Each channel has 1 << W.profile profiles available.
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Each profile stores 8 values, each up to W.coeff bits wide, arranged as:
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[FTW1, B1, POW, CFG, OFFSET, A1, FTW0, B0]
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The lower 8 bits of CFG hold the ADC input channel index SEL.
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The bits from bit 8 up hold the IIR activation delay DLY.
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The back memory is 2*W.coeff bits wide and each value pair
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(even and odd address)
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are stored in a single location with the odd address value occupying the
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high bits.
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State memory
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============
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The filter state consists of the previous ADC input values X1,
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the current ADC input values X0 and the previous output values
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of the IIR filter (Y1). The filter
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state is stored in a dual-port block RAM that can be accessed
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externally.
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Memory Layout
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-------------
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The state memory holds all Y1 values (IIR processor outputs) for all
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profiles of all channels in the lower half (1 << W.profile + W.channel
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addresses) and the pairs of old and new ADC input values X1, and X0,
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in the upper half (1 << W.channel addresses). Each memory location is
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W.state bits wide.
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Real-time control
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=================
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Signals are exposed for each channel:
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* The active profile, PROFILE
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* Whether to perform IIR filter iterations, EN_IIR
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* The RF switch state enabling output from the channel, EN_OUT
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Delayed IIR processing
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======================
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The IIR filter iterations on a given channel are only performed all of the
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following are true:
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* PROFILE, EN_IIR, EN_OUT have not been updated in the within the
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last DLY cycles
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* EN_IIR is asserted
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* EN_OUT is asserted
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DSP design
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==========
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Typical design at the DSP level. This does not include the description of
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the pipelining or the overall latency involved.
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IIRWidths(state=25, coeff=18, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=3, profile=5)
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X0 = ADC * 2^(25 - 1 - 16)
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X1 = X0 delayed by one cycle
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A0 = 2^11
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A0*Y0 = A1*Y1 - B0*(X0 - OFFSET) - B1*(X1 - OFFSET)
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Y1 = Y0 delayed by one cycle
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ASF = Y0 / 2^(25 - 14 - 1)
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ADC: input value from the ADC
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ASF: output amplitude scale factor to DDS
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OFFSET: setpoint
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A0: fixed factor
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A1/B0/B1: coefficients
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B0 --/- A0: 2^11
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18 | |
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ADC -/-[<<]-/-(-)-/---(x)-(+)-/-[>>]-/-[_/^]-/---[>>]-/- ASF
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16 8 24 | 25 | | 48 11 37 25 | 10 15
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OFFSET --/- [z^-1] ^ [z^-1]
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24 | | |
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-(x)-(+)-<-(x)-----<------
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B1 --/- A1 --/-
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18 18
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[<<]: left shift, multiply by 2^n
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[>>]: right shift, divide by 2^n
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(x): multiplication
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(+), (-): addition, subtraction
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[_/^]: clip
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[z^-1]: register, delay by one processing cycle (~1.1 µs)
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--/--: signal with a given bit width always includes a sign bit
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-->--: flow is to the right and down unless otherwise indicated
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"""
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def __init__(self, w):
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self.widths = w
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for i, j in enumerate(w):
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assert j > 0, (i, j, w)
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assert w.word <= w.coeff # same memory
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assert w.state + w.coeff + 3 <= w.accu
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# m_coeff of active profiles should only be accessed during
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# ~processing
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self.specials.m_coeff = Memory(
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width=2*w.coeff, # Cat(pow/ftw/offset, cfg/a/b)
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depth=4 << w.profile + w.channel)
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# m_state[x] should only be read during ~(shifting |
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# loading)
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# m_state[y] of active profiles should only be read during
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# ~processing
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self.specials.m_state = Memory(
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width=w.state, # y1,x0,x1
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depth=(1 << w.profile + w.channel) + (2 << w.channel))
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# ctrl should only be updated synchronously
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self.ctrl = [Record([
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("profile", w.profile),
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("en_out", 1),
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("en_iir", 1),
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("stb", 1)])
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for i in range(1 << w.channel)]
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# only update during ~loading
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self.adc = [Signal((w.adc, True), reset_less=True)
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for i in range(1 << w.channel)]
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# Cat(ftw0, ftw1, pow, asf)
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# only read during ~processing
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self.dds = [Signal(4*w.word, reset_less=True)
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for i in range(1 << w.channel)]
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# perform one IIR iteration, start with loading,
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# then processing, then shifting, end with done
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self.start = Signal()
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# adc inputs being loaded into RAM (becoming x0)
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self.loading = Signal()
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# processing state data (extracting ftw0/ftw1/pow,
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# computing asf/y0, and storing as y1)
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self.processing = Signal()
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# shifting input state values around (x0 becomes x1)
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self.shifting = Signal()
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# iteration done, the next iteration can be started
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self.done = Signal()
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###
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# pivot arrays for muxing
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profiles = Array([ch.profile for ch in self.ctrl])
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en_outs = Array([ch.en_out for ch in self.ctrl])
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en_iirs = Array([ch.en_iir for ch in self.ctrl])
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# state counter
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state = Signal(w.channel + 2)
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# pipeline group activity flags (SR)
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stage = Signal(3)
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self.submodules.fsm = fsm = FSM("IDLE")
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state_clr = Signal()
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stage_en = Signal()
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fsm.act("IDLE",
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self.done.eq(1),
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state_clr.eq(1),
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If(self.start,
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NextState("LOAD")
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)
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)
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fsm.act("LOAD",
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self.loading.eq(1),
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If(state == (1 << w.channel) - 1,
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state_clr.eq(1),
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stage_en.eq(1),
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NextState("PROCESS")
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)
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)
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fsm.act("PROCESS",
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self.processing.eq(1),
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# this is technically wasting three cycles
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# (one for setting stage, and phase=2,3 with stage[2])
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If(stage == 0,
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state_clr.eq(1),
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NextState("SHIFT")
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)
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)
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fsm.act("SHIFT",
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self.shifting.eq(1),
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If(state == (2 << w.channel) - 1,
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NextState("IDLE")
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)
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)
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self.sync += [
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state.eq(state + 1),
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If(state_clr,
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state.eq(0),
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),
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If(stage_en,
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stage[0].eq(1)
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)
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]
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# pipeline group channel pointer
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# for each pipeline stage, this is the channel currently being
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# processed
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channel = [Signal(w.channel, reset_less=True) for i in range(3)]
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# pipeline group profile pointer (SR)
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# for each pipeline stage, this is the profile currently being
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# processed
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profile = [Signal(w.profile, reset_less=True) for i in range(2)]
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# pipeline phase (lower two bits of state)
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phase = Signal(2, reset_less=True)
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self.comb += Cat(phase, channel[0]).eq(state)
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self.sync += [
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Case(phase, {
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0: [
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profile[0].eq(profiles[channel[0]]),
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profile[1].eq(profile[0])
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],
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3: [
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Cat(channel[1:]).eq(Cat(channel[:-1])),
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stage[1:].eq(stage[:-1]),
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If(channel[0] == (1 << w.channel) - 1,
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stage[0].eq(0)
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)
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]
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})
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]
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m_coeff = self.m_coeff.get_port()
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m_state = self.m_state.get_port(write_capable=True)
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self.specials += m_state, m_coeff
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dsp = DSP(w)
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self.submodules += dsp
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offset_clr = Signal()
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self.comb += [
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m_coeff.adr.eq(Cat(phase, profile[0],
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Mux(phase==0, channel[1], channel[0]))),
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dsp.offset[-w.coeff - 1:].eq(Mux(offset_clr, 0,
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Cat(m_coeff.dat_r[:w.coeff], m_coeff.dat_r[w.coeff - 1])
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)),
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dsp.coeff.eq(m_coeff.dat_r[w.coeff:]),
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dsp.state.eq(m_state.dat_r),
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Case(phase, {
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0: dsp.accu_clr.eq(1),
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2: [
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offset_clr.eq(1),
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dsp.offset_load.eq(1)
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],
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3: dsp.offset_load.eq(1)
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})
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]
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# selected adc (combinatorial from dat_r)
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sel_profile = Signal(w.channel)
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# profile delay (combinatorial from dat_r)
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dly_profile = Signal(8)
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# latched adc selection
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sel = Signal(w.channel, reset_less=True)
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# iir enable SR
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en = Signal(2, reset_less=True)
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assert w.channel <= 8
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assert w.profile <= len(dly_profile)
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assert w.profile + 8 <= len(m_coeff.dat_r)
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self.comb += [
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sel_profile.eq(m_coeff.dat_r[w.coeff:]),
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dly_profile.eq(m_coeff.dat_r[w.coeff + 8:]),
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If(self.shifting,
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m_state.adr.eq(state | (1 << w.profile + w.channel)),
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m_state.dat_w.eq(m_state.dat_r),
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m_state.we.eq(state[0])
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),
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If(self.loading,
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m_state.adr.eq((state << 1) | (1 << w.profile + w.channel)),
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m_state.dat_w[-w.adc - 1:-1].eq(Array(self.adc)[state]),
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m_state.dat_w[-1].eq(m_state.dat_w[-2]),
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m_state.we.eq(1)
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),
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If(self.processing,
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m_state.adr.eq(Array([
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# write back new y
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Cat(profile[1], channel[2]),
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# read old y
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Cat(profile[0], channel[0]),
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# x0 (recent)
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0 | (sel_profile << 1) | (1 << w.profile + w.channel),
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# x1 (old)
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1 | (sel << 1) | (1 << w.profile + w.channel),
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])[phase]),
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m_state.dat_w.eq(dsp.output),
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m_state.we.eq((phase == 0) & stage[2] & en[1]),
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)
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]
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# internal channel delay counters
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dlys = Array([Signal(len(dly_profile))
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for i in range(1 << w.channel)])
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self._dlys = dlys # expose for debugging only
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for i in range(1 << w.channel):
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self.sync += [
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# (profile != profile_old) | ~en_out
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If(self.ctrl[i].stb,
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dlys[i].eq(0),
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)
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]
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# latched channel delay
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dly = Signal(len(dly_profile), reset_less=True)
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# latched channel en_out
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en_out = Signal(reset_less=True)
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# latched channel en_iir
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en_iir = Signal(reset_less=True)
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# muxing
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ddss = Array(self.dds)
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self.sync += [
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Case(phase, {
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0: [
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dly.eq(dlys[channel[0]]),
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en_out.eq(en_outs[channel[0]]),
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en_iir.eq(en_iirs[channel[0]]),
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If(stage[1],
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ddss[channel[1]][:w.word].eq(
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m_coeff.dat_r),
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)
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],
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1: [
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If(stage[1],
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ddss[channel[1]][w.word:2*w.word].eq(
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m_coeff.dat_r),
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),
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If(stage[2],
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ddss[channel[2]][3*w.word:].eq(
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m_state.dat_r[w.state - w.asf - 1:w.state - 1])
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)
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],
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2: [
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en[0].eq(0),
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en[1].eq(en[0]),
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sel.eq(sel_profile),
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If(stage[0],
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ddss[channel[0]][2*w.word:3*w.word].eq(
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m_coeff.dat_r),
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If(en_out,
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If(dly != dly_profile,
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dlys[channel[0]].eq(dly + 1)
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).Elif(en_iir,
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en[0].eq(1)
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)
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)
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)
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],
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3: [
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],
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}),
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]
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def _coeff(self, channel, profile, coeff):
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"""Return ``high_word``, ``address`` and bit ``mask`` for the
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storage of coefficient name ``coeff`` in profile ``profile``
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of channel ``channel``.
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``high_word`` determines whether the coefficient is stored in the high
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or low part of the memory location.
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"""
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w = self.widths
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addr = "ftw1 b1 pow cfg offset a1 ftw0 b0".split().index(coeff)
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coeff_addr = ((channel << w.profile + 2) | (profile << 2) |
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(addr >> 1))
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mask = (1 << w.coeff) - 1
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return addr & 1, coeff_addr, mask
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def set_coeff(self, channel, profile, coeff, value):
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"""Set the coefficient value.
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Note that due to two coefficiddents sharing a single memory
|
|
location, only one coefficient update can be effected to a given memory
|
|
location per simulation clock cycle.
|
|
"""
|
|
w = self.widths
|
|
word, addr, mask = self._coeff(channel, profile, coeff)
|
|
val = yield self.m_coeff[addr]
|
|
if word:
|
|
val = (val & mask) | ((value & mask) << w.coeff)
|
|
else:
|
|
val = (value & mask) | (val & (mask << w.coeff))
|
|
yield self.m_coeff[addr].eq(val)
|
|
|
|
def get_coeff(self, channel, profile, coeff):
|
|
"""Get a coefficient value."""
|
|
w = self.widths
|
|
word, addr, mask = self._coeff(channel, profile, coeff)
|
|
val = yield self.m_coeff[addr]
|
|
if word:
|
|
return val >> w.coeff
|
|
else:
|
|
return val & mask
|
|
if val in "offset a1 b0 b1".split():
|
|
val = signed(val, w.coeff)
|
|
return val
|
|
|
|
def set_state(self, channel, val, profile=None, coeff="y1"):
|
|
"""Set a state value."""
|
|
w = self.widths
|
|
if coeff == "y1":
|
|
assert profile is not None
|
|
yield self.m_state[profile | (channel << w.profile)].eq(val)
|
|
elif coeff == "x0":
|
|
assert profile is None
|
|
yield self.m_state[(channel << 1) |
|
|
(1 << w.profile + w.channel)].eq(val)
|
|
elif coeff == "x1":
|
|
assert profile is None
|
|
yield self.m_state[1 | (channel << 1) |
|
|
(1 << w.profile + w.channel)].eq(val)
|
|
else:
|
|
raise ValueError("no such state", coeff)
|
|
|
|
def get_state(self, channel, profile=None, coeff="y1"):
|
|
"""Get a state value."""
|
|
w = self.widths
|
|
if coeff == "y1":
|
|
val = yield self.m_state[profile | (channel << w.profile)]
|
|
elif coeff == "x0":
|
|
val = yield self.m_state[(channel << 1) |
|
|
(1 << w.profile + w.channel)]
|
|
elif coeff == "x1":
|
|
val = yield self.m_state[1 | (channel << 1) |
|
|
(1 << w.profile + w.channel)]
|
|
else:
|
|
raise ValueError("no such state", coeff)
|
|
return signed(val, w.state)
|
|
|
|
def fast_iter(self):
|
|
"""Perform a single processing iteration."""
|
|
assert (yield self.done)
|
|
yield self.start.eq(1)
|
|
yield
|
|
yield self.start.eq(0)
|
|
yield
|
|
while not (yield self.done):
|
|
yield
|
|
|
|
def check_iter(self):
|
|
"""Perform a single processing iteration while verifying
|
|
the behavior."""
|
|
w = self.widths
|
|
|
|
while not (yield self.done):
|
|
yield
|
|
|
|
yield self.start.eq(1)
|
|
yield
|
|
yield self.start.eq(0)
|
|
yield
|
|
assert not (yield self.done)
|
|
assert (yield self.loading)
|
|
while (yield self.loading):
|
|
yield
|
|
|
|
x0s = []
|
|
# check adc loading
|
|
for i in range(1 << w.channel):
|
|
v_adc = signed((yield self.adc[i]), w.adc)
|
|
x0 = yield from self.get_state(i, coeff="x0")
|
|
x0s.append(x0)
|
|
assert v_adc << (w.state - w.adc - 1) == x0, (hex(v_adc), hex(x0))
|
|
logger.debug("adc[%d] adc=%x x0=%x", i, v_adc, x0)
|
|
|
|
data = []
|
|
# predict output
|
|
for i in range(1 << w.channel):
|
|
j = yield self.ctrl[i].profile
|
|
en_iir = yield self.ctrl[i].en_iir
|
|
en_out = yield self.ctrl[i].en_out
|
|
dly_i = yield self._dlys[i]
|
|
logger.debug("ctrl[%d] profile=%d en_iir=%d en_out=%d dly=%d",
|
|
i, j, en_iir, en_out, dly_i)
|
|
|
|
cfg = yield from self.get_coeff(i, j, "cfg")
|
|
k_j = cfg & ((1 << w.channel) - 1)
|
|
dly_j = (cfg >> 8) & 0xff
|
|
logger.debug("cfg[%d,%d] sel=%d dly=%d", i, j, k_j, dly_j)
|
|
|
|
en = en_iir & en_out & (dly_i >= dly_j)
|
|
logger.debug("en[%d,%d] %d", i, j, en)
|
|
|
|
offset = yield from self.get_coeff(i, j, "offset")
|
|
offset <<= w.state - w.coeff - 1
|
|
a1 = yield from self.get_coeff(i, j, "a1")
|
|
b0 = yield from self.get_coeff(i, j, "b0")
|
|
b1 = yield from self.get_coeff(i, j, "b1")
|
|
logger.debug("coeff[%d,%d] offset=%#x a1=%#x b0=%#x b1=%#x",
|
|
i, j, offset, a1, b0, b1)
|
|
|
|
ftw0 = yield from self.get_coeff(i, j, "ftw0")
|
|
ftw1 = yield from self.get_coeff(i, j, "ftw1")
|
|
pow = yield from self.get_coeff(i, j, "pow")
|
|
logger.debug("dds[%d,%d] ftw0=%#x ftw1=%#x pow=%#x",
|
|
i, j, ftw0, ftw1, pow)
|
|
|
|
y1 = yield from self.get_state(i, j, "y1")
|
|
x1 = yield from self.get_state(k_j, coeff="x1")
|
|
x0 = yield from self.get_state(k_j, coeff="x0")
|
|
logger.debug("state y1[%d,%d]=%#x x0[%d]=%#x x1[%d]=%#x",
|
|
i, j, y1, k_j, x0, k_j, x1)
|
|
|
|
p = (0*(1 << w.shift - 1) + a1*(0 - y1) +
|
|
b0*(offset - x0) + b1*(offset - x1))
|
|
out = p >> w.shift
|
|
y0 = min(max(0, out), (1 << w.state - 1) - 1)
|
|
logger.debug("dsp[%d,%d] p=%#x out=%#x y0=%#x",
|
|
i, j, p, out, y0)
|
|
|
|
if not en:
|
|
y0 = y1
|
|
data.append((ftw0, ftw1, pow, y0, x1, x0))
|
|
|
|
# wait for output
|
|
assert (yield self.processing)
|
|
while (yield self.processing):
|
|
yield
|
|
|
|
assert (yield self.shifting)
|
|
while (yield self.shifting):
|
|
yield
|
|
|
|
# check x shifting
|
|
for i, x0 in enumerate(x0s):
|
|
x1 = yield from self.get_state(i, coeff="x1")
|
|
assert x1 == x0, (hex(x1), hex(x0))
|
|
logger.debug("adc[%d] x0=%x x1=%x", i, x0, x1)
|
|
|
|
# check new state
|
|
for i in range(1 << w.channel):
|
|
j = yield self.ctrl[i].profile
|
|
logger.debug("ch[%d] profile=%d", i, j)
|
|
y1 = yield from self.get_state(i, j, "y1")
|
|
ftw0, ftw1, pow, y0, x1, x0 = data[i]
|
|
assert y1 == y0, (hex(y1), hex(y0))
|
|
|
|
# check dds output
|
|
for i in range(1 << w.channel):
|
|
ftw0, ftw1, pow, y0, x1, x0 = data[i]
|
|
asf = y0 >> (w.state - w.asf - 1)
|
|
dds = (ftw0 | (ftw1 << w.word) |
|
|
(pow << 2*w.word) | (asf << 3*w.word))
|
|
dds_state = yield self.dds[i]
|
|
logger.debug("ch[%d] dds_state=%#x dds=%#x", i, dds_state, dds)
|
|
assert dds_state == dds, [hex(_) for _ in
|
|
(dds_state, asf, pow, ftw1, ftw0)]
|
|
|
|
assert (yield self.done)
|
|
return data
|