mirror of https://github.com/m-labs/artiq.git
235 lines
9.0 KiB
Python
235 lines
9.0 KiB
Python
from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg, PulseSynchronizer, Gearbox
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from migen.genlib.misc import BitSlip
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from misoc.cores.code_8b10b import Encoder, Decoder
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class KUSSerdes(Module):
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def __init__(self, pll, pads, mode="master"):
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self.tx_k = Signal(4)
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self.tx_d = Signal(32)
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self.rx_k = Signal(4)
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self.rx_d = Signal(32)
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self.tx_idle = Signal()
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self.tx_comma = Signal()
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self.rx_idle = Signal()
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self.rx_comma = Signal()
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self.rx_bitslip_value = Signal(6)
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self.rx_delay_rst = Signal()
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self.rx_delay_inc = Signal()
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self.rx_delay_ce = Signal()
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self.rx_delay_en_vtc = Signal()
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# # #
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self.submodules.encoder = ClockDomainsRenamer("serwb_serdes")(
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Encoder(4, True))
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self.decoders = [ClockDomainsRenamer("serwb_serdes")(
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Decoder(True)) for _ in range(4)]
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self.submodules += self.decoders
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# clocking:
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# In master mode:
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# - linerate/10 pll refclk provided by user
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# - linerate/10 slave refclk generated on clk_pads
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# In Slave mode:
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# - linerate/10 pll refclk provided by clk_pads
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self.clock_domains.cd_serwb_serdes = ClockDomain()
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self.clock_domains.cd_serwb_serdes_5x = ClockDomain()
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self.clock_domains.cd_serwb_serdes_20x = ClockDomain(reset_less=True)
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self.comb += [
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self.cd_serwb_serdes.clk.eq(pll.serwb_serdes_clk),
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self.cd_serwb_serdes_5x.clk.eq(pll.serwb_serdes_5x_clk),
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self.cd_serwb_serdes_20x.clk.eq(pll.serwb_serdes_20x_clk)
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]
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self.specials += AsyncResetSynchronizer(self.cd_serwb_serdes, ~pll.lock)
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self.specials += AsyncResetSynchronizer(self.cd_serwb_serdes_5x, ~pll.lock)
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# control/status cdc
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tx_idle = Signal()
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tx_comma = Signal()
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rx_idle = Signal()
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rx_comma = Signal()
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rx_bitslip_value = Signal(6)
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rx_delay_rst = Signal()
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rx_delay_inc = Signal()
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rx_delay_en_vtc = Signal()
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rx_delay_ce = Signal()
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self.specials += [
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MultiReg(self.tx_idle, tx_idle, "serwb_serdes"),
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MultiReg(self.tx_comma, tx_comma, "serwb_serdes"),
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MultiReg(rx_idle, self.rx_idle, "sys"),
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MultiReg(rx_comma, self.rx_comma, "sys"),
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MultiReg(self.rx_bitslip_value, rx_bitslip_value, "serwb_serdes"),
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MultiReg(self.rx_delay_inc, rx_delay_inc, "serwb_serdes_5x"),
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MultiReg(self.rx_delay_en_vtc, rx_delay_en_vtc, "serwb_serdes_5x")
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]
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self.submodules.do_rx_delay_rst = PulseSynchronizer("sys", "serwb_serdes_5x")
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self.comb += [
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rx_delay_rst.eq(self.do_rx_delay_rst.o),
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self.do_rx_delay_rst.i.eq(self.rx_delay_rst)
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]
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self.submodules.do_rx_delay_ce = PulseSynchronizer("sys", "serwb_serdes_5x")
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self.comb += [
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rx_delay_ce.eq(self.do_rx_delay_ce.o),
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self.do_rx_delay_ce.i.eq(self.rx_delay_ce)
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]
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# tx clock (linerate/10)
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if mode == "master":
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self.submodules.tx_clk_gearbox = Gearbox(40, "serwb_serdes", 8, "serwb_serdes_5x")
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self.comb += self.tx_clk_gearbox.i.eq((0b1111100000 << 30) |
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(0b1111100000 << 20) |
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(0b1111100000 << 10) |
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(0b1111100000 << 0))
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clk_o = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_DATA_WIDTH=8, p_INIT=0,
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p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
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o_OQ=clk_o,
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i_RST=ResetSignal("serwb_serdes"),
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i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKDIV=ClockSignal("serwb_serdes_5x"),
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i_D=self.tx_clk_gearbox.o
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),
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Instance("OBUFDS",
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i_I=clk_o,
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o_O=pads.clk_p,
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o_OB=pads.clk_n
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)
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]
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# tx datapath
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# tx_data -> encoders -> gearbox -> serdes
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self.submodules.tx_gearbox = Gearbox(40, "serwb_serdes", 8, "serwb_serdes_5x")
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self.comb += [
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If(tx_comma,
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(0xbc)
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).Else(
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self.encoder.k[0].eq(self.tx_k[0]),
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self.encoder.k[1].eq(self.tx_k[1]),
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self.encoder.k[2].eq(self.tx_k[2]),
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self.encoder.k[3].eq(self.tx_k[3]),
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self.encoder.d[0].eq(self.tx_d[0:8]),
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self.encoder.d[1].eq(self.tx_d[8:16]),
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self.encoder.d[2].eq(self.tx_d[16:24]),
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self.encoder.d[3].eq(self.tx_d[24:32])
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)
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]
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self.sync.serwb_serdes += \
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If(tx_idle,
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self.tx_gearbox.i.eq(0)
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).Else(
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self.tx_gearbox.i.eq(Cat(*[self.encoder.output[i] for i in range(4)]))
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)
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serdes_o = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_DATA_WIDTH=8, p_INIT=0,
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p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
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o_OQ=serdes_o,
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i_RST=ResetSignal("serwb_serdes"),
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i_CLK=ClockSignal("serwb_serdes_20x"), i_CLKDIV=ClockSignal("serwb_serdes_5x"),
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i_D=self.tx_gearbox.o
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),
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Instance("OBUFDS",
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i_I=serdes_o,
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o_O=pads.tx_p,
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o_OB=pads.tx_n
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)
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]
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# rx clock
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use_bufr = True
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if mode == "slave":
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clk_i = Signal()
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clk_i_bufg = Signal()
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self.specials += [
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Instance("IBUFDS",
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i_I=pads.clk_p,
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i_IB=pads.clk_n,
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o_O=clk_i
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)
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]
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if use_bufr:
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clk_i_bufr = Signal()
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self.specials += [
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Instance("BUFR", i_I=clk_i, o_O=clk_i_bufr),
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Instance("BUFG", i_I=clk_i_bufr, o_O=clk_i_bufg)
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]
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else:
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self.specials += Instance("BUFG", i_I=clk_i, o_O=clk_i_bufg)
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self.comb += pll.refclk.eq(clk_i_bufg)
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# rx datapath
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# serdes -> gearbox -> bitslip -> decoders -> rx_data
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self.submodules.rx_gearbox = Gearbox(8, "serwb_serdes_5x", 40, "serwb_serdes")
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self.submodules.rx_bitslip = ClockDomainsRenamer("serwb_serdes")(BitSlip(40))
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serdes_i_nodelay = Signal()
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self.specials += [
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Instance("IBUFDS_DIFF_OUT",
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i_I=pads.rx_p,
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i_IB=pads.rx_n,
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o_O=serdes_i_nodelay
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)
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]
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serdes_i_delayed = Signal()
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serdes_q = Signal(8)
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self.specials += [
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Instance("IDELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0,
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p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
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p_DELAY_FORMAT="COUNT", p_DELAY_SRC="IDATAIN",
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p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
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i_CLK=ClockSignal("serwb_serdes_5x"),
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i_RST=rx_delay_rst, i_LOAD=0,
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i_INC=rx_delay_inc, i_EN_VTC=rx_delay_en_vtc,
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i_CE=rx_delay_ce,
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i_IDATAIN=serdes_i_nodelay, o_DATAOUT=serdes_i_delayed
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),
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Instance("ISERDESE3",
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p_IS_CLK_INVERTED=0,
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p_IS_CLK_B_INVERTED=1,
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p_DATA_WIDTH=8,
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i_D=serdes_i_delayed,
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i_RST=ResetSignal("serwb_serdes"),
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i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("serwb_serdes_20x"),
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i_CLK_B=ClockSignal("serwb_serdes_20x"), # locally inverted
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i_CLKDIV=ClockSignal("serwb_serdes_5x"),
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o_Q=serdes_q
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)
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]
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self.comb += [
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self.rx_gearbox.i.eq(serdes_q),
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self.rx_bitslip.value.eq(rx_bitslip_value),
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self.rx_bitslip.i.eq(self.rx_gearbox.o),
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self.decoders[0].input.eq(self.rx_bitslip.o[0:10]),
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self.decoders[1].input.eq(self.rx_bitslip.o[10:20]),
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self.decoders[2].input.eq(self.rx_bitslip.o[20:30]),
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self.decoders[3].input.eq(self.rx_bitslip.o[30:40]),
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self.rx_k.eq(Cat(*[self.decoders[i].k for i in range(4)])),
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self.rx_d.eq(Cat(*[self.decoders[i].d for i in range(4)])),
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rx_idle.eq(self.rx_bitslip.o == 0),
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rx_comma.eq(((self.decoders[0].d == 0xbc) & (self.decoders[0].k == 1)) &
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((self.decoders[1].d == 0x00) & (self.decoders[1].k == 0)) &
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((self.decoders[2].d == 0x00) & (self.decoders[2].k == 0)) &
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((self.decoders[3].d == 0x00) & (self.decoders[3].k == 0)))
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]
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