mirror of https://github.com/m-labs/artiq.git
74 lines
2.1 KiB
Python
74 lines
2.1 KiB
Python
from migen import *
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from artiq.gateware.rtio import rtlink
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def fifo_payload(channels):
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address_width = max(rtlink.get_address_width(channel.interface)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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for channel in channels)
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layout = [
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("channel", bits_for(len(channels)-1)),
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("timestamp", 64)
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]
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if address_width:
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layout.append(("address", address_width))
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if data_width:
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layout.append(("data", data_width))
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return layout
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def seqn_width(lane_count, fifo_width):
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# There must be a unique sequence number for every possible event in every FIFO.
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# Plus 2 bits to detect and handle wraparounds.
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return bits_for(lane_count*fifo_size-1) + 2
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def fifo_ingress(seqn_width, layout_payload):
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return [
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("we", 1, DIR_M_TO_S),
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("writable", 1, DIR_S_TO_M),
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("seqn", seqn_width, DIR_M_TO_S),
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("payload", [(a, b, DIR_M_TO_S) for a, b in layout_payload])
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]
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def fifo_egress(seqn_width, layout_payload):
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return [
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("re", 1, DIR_S_TO_M),
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("readable", 1, DIR_M_TO_S),
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("seqn", seqn_width, DIR_M_TO_S),
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("payload", [(a, b, DIR_M_TO_S) for a, b in layout_payload])
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]
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def output_network_payload(channels):
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fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface)
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for channel in channels)
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address_width = max(rtlink.get_address_width(channel.interface)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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for channel in channels)
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layout = [("channel", bits_for(len(channels)-1))]
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if fine_ts_width:
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layout.append(("fine_ts", fine_ts_width))
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if address_width:
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layout.append(("address", address_width))
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if data_width:
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layout.append(("data", data_width))
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return layout
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def output_network_node(seqn_width, layout_payload):
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return [
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("valid", 1),
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("seqn", seqn_width),
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("replace_occured", 1),
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("payload", layout_payload)
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]
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