mirror of https://github.com/m-labs/artiq.git
70 lines
2.6 KiB
Python
70 lines
2.6 KiB
Python
"""Protocol error reporting for satellites."""
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from migen import *
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import BlindTransfer
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class RTErrorsSatellite(Module, AutoCSR):
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def __init__(self, rt_packet, outputs):
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self.protocol_error = CSR(4)
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self.rtio_error = CSR(3)
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self.sequence_error_channel = CSRStatus(16)
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self.collision_channel = CSRStatus(16)
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self.busy_channel = CSRStatus(16)
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def error_csr(csr, *sources):
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for n, (source, detect_edges, din, dout) in enumerate(sources):
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assert isinstance(source, Signal)
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if din is not None:
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data_width = len(din)
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else:
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data_width = 0
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xfer = BlindTransfer(odomain="sys", data_width=data_width)
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self.submodules += xfer
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if detect_edges:
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source_r = Signal()
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self.sync.rio += source_r.eq(source)
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self.comb += xfer.i.eq(source & ~source_r)
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else:
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self.comb += xfer.i.eq(source)
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pending = Signal(related=source)
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self.sync += [
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If(csr.re & csr.r[n], pending.eq(0)),
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If(xfer.o, pending.eq(1))
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]
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self.comb += csr.w[n].eq(pending)
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if din is not None:
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self.comb += xfer.data_i.eq(din)
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self.sync += If(xfer.o & ~pending, dout.eq(xfer.data_o))
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# The master is normally responsible for avoiding output overflows
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# and output underflows. The error reports here are only for diagnosing
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# internal ARTIQ bugs.
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underflow = Signal()
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overflow = Signal()
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self.comb += [
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underflow.eq(outputs.cri.o_status[1]),
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overflow.eq(outputs.cri.o_status[0])
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]
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error_csr(self.protocol_error,
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(rt_packet.unknown_packet_type, False, None, None),
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(rt_packet.packet_truncated, False, None, None),
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(underflow, True, None, None),
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(overflow, True, None, None)
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)
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error_csr(self.rtio_error,
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(outputs.sequence_error, False,
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outputs.sequence_error_channel, self.sequence_error_channel.status),
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(outputs.collision, False,
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outputs.collision_channel, self.collision_channel.status),
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(outputs.busy, False,
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outputs.busy_channel, self.busy_channel.status)
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)
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