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406 lines
15 KiB
Python
406 lines
15 KiB
Python
from fractions import Fraction
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.record import Record
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from migen.genlib.cdc import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from artiqlib.rtio.rbus import get_fine_ts_width
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class _GrayCodeTransfer(Module):
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def __init__(self, width):
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self.i = Signal(width) # in rio domain
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self.o = Signal(width) # in rsys domain
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# # #
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# convert to Gray code
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value_gray_rio = Signal(width)
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self.sync.rio += value_gray_rio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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self.specials += [
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NoRetiming(value_gray_rio),
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MultiReg(value_gray_rio, value_gray_sys, "rsys")
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]
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# convert back to binary
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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for i in reversed(range(width-1)):
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self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
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self.sync.rsys += self.o.eq(value_sys)
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class _RTIOCounter(Module):
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def __init__(self, width, loopback_latency):
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self.width = width
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# Timestamp counter in RTIO domain for outputs
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self.o_value_rio = Signal(width)
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# Timestamp counter resynchronized to sys domain
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# Lags behind o_value_rio, monotonic and glitch-free
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self.o_value_sys = Signal(width)
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# Timestamp counter in RTIO domain for inputs,
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# compensated for PHY loopback latency
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self.i_value_rio = Signal(width, reset=2**width-loopback_latency)
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# # #
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self.sync.rio += [
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self.o_value_rio.eq(self.o_value_rio + 1),
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self.i_value_rio.eq(self.i_value_rio + 1)
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]
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gt = _GrayCodeTransfer(width)
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self.submodules += gt
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self.comb += gt.i.eq(self.o_value_rio), self.o_value_sys.eq(gt.o)
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# CHOOSING A GUARD TIME
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#
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# The buffer must be transferred to the FIFO soon enough to account for:
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# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
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# * FIFO latency: Tsys + 2*Tio
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# * FIFO buffer latency: Tio
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# Therefore we must choose:
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# guard_io_cycles > (4*Tio + 4*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached. This can fill the FIFO and deassert the writable flag. A race
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# condition occurs that causes problems if the deassertion happens between
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# the CPU checking the writable flag (and reading 1) and writing a new event.
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#
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# When the FIFO is about to be full, it contains fifo_depth-1 events of
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# strictly increasing timestamps.
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#
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# Thus the FIFO-filling event's timestamp must satisfy:
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# timestamp*Tio > (fifo_depth-1)*Tio + time
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# We also have (guard time reached):
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# timestamp*Tio < time + guard_io_cycles*Tio
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# [NB: time > counter.o_value_sys*Tio]
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# Thus we must have:
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# guard_io_cycles > fifo_depth-1
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#
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# We can prevent overflows by choosing instead:
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# guard_io_cycles < fifo_depth-1
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth, guard_io_cycles):
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self.sel = Signal(max=len(rbus))
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# timestamp and value must be valid 1 cycle before we
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self.timestamp = Signal(counter.width + fine_ts_width)
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self.value = Signal(2)
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self.writable = Signal()
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self.we = Signal() # maximum throughput 1/2
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self.underflow = Signal() # valid 2 cycles after we
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self.underflow_reset = Signal()
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self.sequence_error = Signal()
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self.sequence_error_reset = Signal()
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# # #
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signal_underflow = Signal()
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signal_sequence_error = Signal()
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fifos = []
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ev_layout = [("timestamp", counter.width + fine_ts_width),
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("value", 2)]
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for n, chif in enumerate(rbus):
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# FIFO
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fifo = RenameClockDomains(AsyncFIFO(ev_layout, fifo_depth),
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{"write": "rsys", "read": "rio"})
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self.submodules += fifo
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fifos.append(fifo)
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# Buffer
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buf_pending = Signal()
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buf = Record(ev_layout)
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buf_just_written = Signal()
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# Special cases
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replace = Signal()
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sequence_error = Signal()
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nop = Signal()
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self.sync.rsys += [
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replace.eq(self.timestamp == buf.timestamp[fine_ts_width:]),
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sequence_error.eq(self.timestamp < buf.timestamp[fine_ts_width:]),
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nop.eq(self.value == buf.value)
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]
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self.comb += If(self.we & (self.sel == n) & sequence_error,
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signal_sequence_error.eq(1))
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# Buffer read and FIFO write
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self.comb += fifo.din.eq(buf)
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in_guard_time = Signal()
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self.comb += in_guard_time.eq(
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buf.timestamp[fine_ts_width:] < counter.o_value_sys + guard_io_cycles)
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self.sync.rsys += If(in_guard_time, buf_pending.eq(0))
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self.comb += \
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If(buf_pending,
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If(in_guard_time,
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If(buf_just_written,
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signal_underflow.eq(1)
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).Else(
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fifo.we.eq(1)
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)
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),
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If((self.we & (self.sel == n)
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& ~replace & ~nop & ~sequence_error),
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fifo.we.eq(1)
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)
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)
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# Buffer write
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# Must come after read to handle concurrent read+write properly
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self.sync.rsys += [
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buf_just_written.eq(0),
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If(self.we & (self.sel == n) & ~nop & ~sequence_error,
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buf_just_written.eq(1),
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buf_pending.eq(1),
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buf.timestamp.eq(self.timestamp),
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buf.value.eq(self.value)
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)
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]
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# Buffer output of FIFO to improve timing
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dout_stb = Signal()
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dout_ack = Signal()
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dout = Record(ev_layout)
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self.sync.rio += \
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If(fifo.re,
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dout_stb.eq(1),
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dout.eq(fifo.dout)
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).Elif(dout_ack,
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dout_stb.eq(0)
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)
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self.comb += fifo.re.eq(fifo.readable & (~dout_stb | dout_ack))
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# FIFO read through buffer
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self.comb += [
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dout_ack.eq(
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dout.timestamp[fine_ts_width:] == counter.o_value_rio),
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chif.o_stb.eq(dout_stb & dout_ack),
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chif.o_value.eq(dout.value)
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]
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if fine_ts_width:
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self.comb += chif.o_fine_ts.eq(
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dout.timestamp[:fine_ts_width])
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self.comb += \
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self.writable.eq(Array(fifo.writable for fifo in fifos)[self.sel])
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self.sync.rsys += [
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If(self.underflow_reset, self.underflow.eq(0)),
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If(self.sequence_error_reset, self.sequence_error.eq(0)),
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If(signal_underflow, self.underflow.eq(1)),
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If(signal_sequence_error, self.sequence_error.eq(1))
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]
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class _RTIOBankI(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter.width + fine_ts_width)
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self.value = Signal()
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal()
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self.overflow_reset = Signal()
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self.pileup_count = Signal(16)
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self.pileup_reset = Signal()
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# # #
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timestamps = []
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values = []
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readables = []
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overflows = []
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pileup_counts = []
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ev_layout = [("timestamp", counter.width+fine_ts_width),
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("value", 1)]
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for n, chif in enumerate(rbus):
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if hasattr(chif, "oe"):
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sensitivity = Signal(2)
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self.sync.rio += If(~chif.oe & chif.o_stb,
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sensitivity.eq(chif.o_value))
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fifo = RenameClockDomains(AsyncFIFO(ev_layout, fifo_depth),
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{"read": "rsys", "write": "rio"})
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self.submodules += fifo
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# FIFO write
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if fine_ts_width:
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full_ts = Cat(chif.i_fine_ts, counter.i_value_rio)
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else:
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full_ts = counter.i_value_rio
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self.comb += [
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fifo.din.timestamp.eq(full_ts),
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fifo.din.value.eq(chif.i_value),
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fifo.we.eq(
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~chif.oe & chif.i_stb &
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((chif.i_value & sensitivity[0])
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| (~chif.i_value & sensitivity[1])))
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]
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# FIFO read
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timestamps.append(fifo.dout.timestamp)
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values.append(fifo.dout.value)
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readables.append(fifo.readable)
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self.comb += fifo.re.eq(self.re & (self.sel == n))
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overflow = Signal()
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overflow_reset_sync = PulseSynchronizer("rsys", "rio")
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self.submodules += overflow_reset_sync
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self.comb += overflow_reset_sync.i.eq(
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self.overflow_reset & (self.sel == n))
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self.sync.rio += [
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If(overflow_reset_sync.o, overflow.eq(0)),
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If(fifo.we & ~fifo.writable, overflow.eq(1))
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]
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overflow_sys = Signal()
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self.specials += MultiReg(overflow, overflow_sys, "rsys")
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overflows.append(overflow_sys)
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pileup_count = Signal(16)
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pileup_count_reset_sync = PulseSynchronizer("rsys", "rio")
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self.submodules += pileup_count_reset_sync
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self.comb += pileup_count_reset_sync.i.eq(
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self.pileup_reset & (self.sel == n))
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self.sync.rio += \
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If(pileup_count_reset_sync.o,
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pileup_count.eq(0)
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).Elif(chif.i_pileup,
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If(pileup_count != 2**16 - 1, # saturate
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pileup_count.eq(pileup_count + 1)
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)
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)
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pileup_count_sync = _GrayCodeTransfer(16)
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self.submodules += pileup_count_sync
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self.comb += pileup_count_sync.i.eq(pileup_count)
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pileup_counts.append(pileup_count_sync.o)
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else:
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timestamps.append(0)
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values.append(0)
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readables.append(0)
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overflows.append(0)
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pileup_counts.append(0)
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self.comb += [
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self.timestamp.eq(Array(timestamps)[self.sel]),
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self.value.eq(Array(values)[self.sel]),
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self.readable.eq(Array(readables)[self.sel]),
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self.overflow.eq(Array(overflows)[self.sel]),
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self.pileup_count.eq(Array(pileup_counts)[self.sel])
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]
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, clk_freq, counter_width=32,
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ofifo_depth=64, ififo_depth=64,
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guard_io_cycles=20):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Submodules
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self.submodules.counter = _RTIOCounter(
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counter_width, phy.loopback_latency)
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self.submodules.bank_o = _RTIOBankO(
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phy.rbus, self.counter, fine_ts_width, ofifo_depth, guard_io_cycles)
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self.submodules.bank_i = _RTIOBankI(
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phy.rbus, self.counter, fine_ts_width, ififo_depth)
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width + fine_ts_width)
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self._r_o_value = CSRStorage(2)
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self._r_o_we = CSR()
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self._r_o_status = CSRStatus(3)
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self._r_o_underflow_reset = CSR()
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self._r_o_sequence_error_reset = CSR()
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self._r_i_timestamp = CSRStatus(counter_width + fine_ts_width)
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self._r_i_value = CSRStatus()
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self._r_i_re = CSR()
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self._r_i_status = CSRStatus(2)
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self._r_i_overflow_reset = CSR()
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self._r_i_pileup_count = CSRStatus(16)
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self._r_i_pileup_reset = CSR()
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self._r_counter = CSRStatus(counter_width + fine_ts_width)
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self._r_counter_update = CSR()
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self._r_frequency_i = CSRStatus(32)
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self._r_frequency_fn = CSRStatus(8)
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self._r_frequency_fd = CSRStatus(8)
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# Clocking/Reset
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# Create rsys and rio domains based on sys and rio
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# with reset controlled by CSR.
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(self._r_reset.storage)
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio, self._r_reset.storage)
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# OE
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oes = []
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for n, chif in enumerate(phy.rbus):
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if hasattr(chif, "oe"):
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self.sync += \
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If(self._r_oe.re & (self._r_chan_sel.storage == n),
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chif.oe.eq(self._r_oe.r)
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)
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oes.append(chif.oe)
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else:
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oes.append(1)
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self.comb += self._r_oe.w.eq(Array(oes)[self._r_chan_sel.storage])
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# Output/Gate
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self.comb += [
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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self.bank_o.we.eq(self._r_o_we.re),
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self._r_o_status.status.eq(Cat(~self.bank_o.writable,
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self.bank_o.underflow,
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self.bank_o.sequence_error)),
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self.bank_o.underflow_reset.eq(self._r_o_underflow_reset.re),
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self.bank_o.sequence_error_reset.eq(self._r_o_sequence_error_reset.re)
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]
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# Input
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self.comb += [
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self.bank_i.sel.eq(self._r_chan_sel.storage),
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self._r_i_timestamp.status.eq(self.bank_i.timestamp),
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self._r_i_value.status.eq(self.bank_i.value),
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self.bank_i.re.eq(self._r_i_re.re),
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self._r_i_status.status.eq(Cat(~self.bank_i.readable, self.bank_i.overflow)),
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self.bank_i.overflow_reset.eq(self._r_i_overflow_reset.re),
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self._r_i_pileup_count.status.eq(self.bank_i.pileup_count),
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self.bank_i.pileup_reset.eq(self._r_i_pileup_reset.re)
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]
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# Counter access
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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self.counter.o_value_sys))
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)
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# Frequency
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clk_freq = Fraction(clk_freq).limit_denominator(255)
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clk_freq_i = int(clk_freq)
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clk_freq_f = clk_freq - clk_freq_i
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self.comb += [
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self._r_frequency_i.status.eq(clk_freq_i),
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self._r_frequency_fn.status.eq(clk_freq_f.numerator),
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self._r_frequency_fd.status.eq(clk_freq_f.denominator)
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]
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