mirror of https://github.com/m-labs/artiq.git
68 lines
2.2 KiB
Rust
68 lines
2.2 KiB
Rust
#[cfg(has_converter_spi)]
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mod imp {
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use board::csr;
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pub fn set_config(busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
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if busno != 0 {
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return Err(())
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}
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
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csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
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csr::converter_spi::clk_phase_write(flags >> 5 & 1);
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csr::converter_spi::lsb_first_write(flags >> 6 & 1);
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csr::converter_spi::half_duplex_write(flags >> 7 & 1);
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csr::converter_spi::clk_div_write_write(write_div);
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csr::converter_spi::clk_div_read_write(read_div);
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csr::converter_spi::offline_write(0);
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}
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Ok(())
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}
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pub fn set_xfer(busno: u8, chip_select: u16, write_length: u8, read_length: u8)
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-> Result<(), ()> {
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if busno != 0 {
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return Err(())
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}
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unsafe {
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csr::converter_spi::cs_write(chip_select as _);
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csr::converter_spi::xfer_len_write_write(write_length);
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csr::converter_spi::xfer_len_read_write(read_length);
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}
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Ok(())
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}
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pub fn write(busno: u8, data: u32) -> Result<(), ()> {
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if busno != 0 {
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return Err(())
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}
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unsafe {
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csr::converter_spi::data_write_write(data);
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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Ok(())
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}
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pub fn read(busno: u8) -> Result<u32, ()> {
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if busno != 0 {
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return Err(())
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}
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Ok(unsafe {
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csr::converter_spi::data_read_read()
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})
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}
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}
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#[cfg(not(has_converter_spi))]
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mod imp {
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pub fn set_config(_busno: u8, _flags: u8, _write_div: u8, _read_div: u8) -> Result<(), ()> { Err(()) }
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pub fn set_xfer(_busno: u8,_chip_select: u16, _write_length: u8, _read_length: u8)
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-> Result<(), ()> { Err(()) }
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pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
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pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
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}
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pub use self::imp::*;
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