mirror of https://github.com/m-labs/artiq.git
148 lines
6.0 KiB
Python
148 lines
6.0 KiB
Python
from types import SimpleNamespace
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from migen import *
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from migen.genlib.cdc import ElasticBuffer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.sed.core import *
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from artiq.gateware.rtio.input_collector import *
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from artiq.gateware.drtio import (link_layer, aux_controller,
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rt_packet_satellite, rt_errors_satellite,
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rt_packet_master, rt_controller_master)
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class ChannelInterface:
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def __init__(self, encoder, decoders):
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self.rx_ready = Signal()
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self.encoder = encoder
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self.decoders = decoders
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class TransceiverInterface(AutoCSR):
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def __init__(self, channel_interfaces):
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self.stable_clkin = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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for i in range(len(channel_interfaces)):
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name = "rtio_rx" + str(i)
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setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
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self.channels = channel_interfaces
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class GenericRXSynchronizer(Module):
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"""Simple RX synchronizer based on the portable Migen elastic buffer.
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Introduces timing non-determinism in the satellite -> master path,
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(and in the echo_request/echo_reply RTT) but useful for testing.
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"""
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def __init__(self):
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self.signals = []
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def resync(self, signal):
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synchronized = Signal.like(signal, related=signal)
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self.signals.append((signal, synchronized))
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return synchronized
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def do_finalize(self):
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eb = ElasticBuffer(sum(len(s[0]) for s in self.signals), 4, "rtio_rx", "rtio")
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self.submodules += eb
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self.comb += [
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eb.din.eq(Cat(*[s[0] for s in self.signals])),
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Cat(*[s[1] for s in self.signals]).eq(eb.dout)
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]
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class DRTIOSatellite(Module):
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def __init__(self, chanif, channels, rx_synchronizer=None, fine_ts_width=3,
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lane_count=8, fifo_depth=128):
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if rx_synchronizer is None:
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rx_synchronizer = GenericRXSynchronizer()
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self.submodules += rx_synchronizer
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx_aux_frame,
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tx_aux_data=self.link_layer.tx_aux_data,
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tx_aux_ack=self.link_layer.tx_aux_ack,
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tx_rt_frame=self.link_layer.tx_rt_frame,
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tx_rt_data=self.link_layer.tx_rt_data,
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rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb),
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rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame),
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rx_aux_frame_perm=rx_synchronizer.resync(self.link_layer.rx_aux_frame_perm),
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rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data),
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rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame),
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rx_rt_frame_perm=rx_synchronizer.resync(self.link_layer.rx_rt_frame_perm),
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rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)
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)
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self.submodules.link_stats = link_layer.LinkLayerStats(link_layer_sync, "rtio")
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self.submodules.rt_packet = ClockDomainsRenamer("rtio")(
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rt_packet_satellite.RTPacketSatellite(link_layer_sync))
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coarse_ts = Signal(64 - fine_ts_width)
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self.sync.rtio += \
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If(self.rt_packet.tsc_load,
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coarse_ts.eq(self.rt_packet.tsc_load_value)
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).Else(
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coarse_ts.eq(coarse_ts + 1)
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)
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self.comb += self.rt_packet.cri.counter.eq(coarse_ts << fine_ts_width)
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self.submodules.outputs = ClockDomainsRenamer("rio")(
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SED(channels, fine_ts_width, "sync",
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lane_count=lane_count, fifo_depth=fifo_depth,
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enable_spread=False, report_buffer_space=True,
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interface=self.rt_packet.cri))
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self.comb += self.outputs.coarse_timestamp.eq(coarse_ts)
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self.sync += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16)
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self.submodules.inputs = ClockDomainsRenamer("rio")(
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InputCollector(channels, fine_ts_width, "sync",
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interface=self.rt_packet.cri))
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self.comb += self.inputs.coarse_timestamp.eq(coarse_ts)
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self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite(
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self.rt_packet, self.outputs)
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio.rst.eq(self.rt_packet.reset),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.rst.eq(self.rt_packet.reset_phy),
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]
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return (self.link_layer.get_csrs() + self.link_stats.get_csrs() +
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self.rt_errors.get_csrs() + self.aux_controller.get_csrs())
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class DRTIOMaster(Module):
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def __init__(self, chanif, channel_count=1024, fine_ts_width=3):
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller_master.RTController(
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self.rt_packet, channel_count, fine_ts_width)
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self.submodules.rt_manager = rt_controller_master.RTManager(self.rt_packet)
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self.cri = self.rt_controller.cri
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.link_stats.get_csrs() +
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self.rt_controller.get_csrs() +
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self.rt_manager.get_csrs() +
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self.aux_controller.get_csrs())
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