mirror of https://github.com/m-labs/artiq.git
Robert Jördens
c63fa46430
* phaser2: (157 commits) sawg/hbf: tweak pipeline for timing fir: register multiplier output conda/phaser: build-depend on numpy sawg: reduce coefficient width sawg: fix latency test/fir: needs mpl. don't run by default test/sawg: patch spline sawg: use ParallelHBFCascade to AA [WIP] fir: add ParallelHBFCascade fir: add ParallelFIR and test gateware/dsp: add FIR and test README_PHASER: update sawg: documentation sawg: extract spline sawg: document sawg: demo_2tone sawg: round to int64 gateware/phaser -> gateware/ad9154_fmc_ebz phaser: fix typo sawg: merge set/set64 ... |
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