mirror of https://github.com/m-labs/artiq.git
45 lines
1.8 KiB
Python
45 lines
1.8 KiB
Python
from migen import *
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from misoc.cores import timer
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from misoc.interconnect import wishbone
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from artiq.gateware.amp.kernel_cpu import KernelCPU
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from artiq.gateware.amp.mailbox import Mailbox
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class AMPSoC:
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"""Contains kernel CPU and mailbox for ARTIQ SoCs.
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Users must provide a "mailbox" entry in the memory map.
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"""
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def __init__(self):
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if not hasattr(self, "cpu"):
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raise ValueError("Platform SoC must be initialized first")
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self.submodules.kernel_cpu = KernelCPU(self.platform)
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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self.csr_devices.append("kernel_cpu")
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mailbox_size = 3
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self.csr_separation = self.kernel_cpu.cpu_dw//8
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self.submodules.mailbox = Mailbox(mailbox_size, adr_width=32-log2_int(self.csr_separation))
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self.add_wb_slave(self.mem_map["mailbox"], self.csr_separation*mailbox_size,
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self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], self.csr_separation*mailbox_size,
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self.mailbox.i2)
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self.add_memory_region("mailbox",
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self.mem_map["mailbox"] | 0x80000000,
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self.csr_separation*mailbox_size)
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def register_kernel_cpu_csrdevice(self, name, csrs=None):
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if csrs is None:
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csrs = getattr(self, name).get_csrs()
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csr_bus = wishbone.Interface(data_width=32, adr_width=32-log2_int(self.csr_separation))
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bank = wishbone.CSRBank(csrs, bus=csr_bus)
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self.config["kernel_has_"+name] = None
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self.submodules += bank
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self.kernel_cpu.add_wb_slave(self.mem_map[name], self.csr_separation*2**bank.decode_bits, bank.bus)
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self.add_csr_region(name,
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self.mem_map[name] | 0x80000000, 32,
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csrs)
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