mirror of https://github.com/m-labs/artiq.git
39 lines
1.5 KiB
Python
39 lines
1.5 KiB
Python
from migen import *
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["Gates"]
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class Gates(Module):
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def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
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self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))
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for _ in range(lane_count)]
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self.output = [Record(layouts.output_network_node(seqn_width, layout_output_network_payload))
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for _ in range(lane_count)]
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if hasattr(self.output[0].payload, "fine_ts"):
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glbl_fine_ts_width = len(self.output[0].payload.fine_ts)
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else:
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glbl_fine_ts_width = 0
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self.coarse_timestamp = Signal(64-glbl_fine_ts_width)
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# # #
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for input, output in zip(self.input, self.output):
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for field, _ in output.payload.layout:
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if field == "fine_ts":
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self.sync += output.payload.fine_ts.eq(input.payload.timestamp[:glbl_fine_ts_width])
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else:
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self.sync += getattr(output.payload, field).eq(getattr(input.payload, field))
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self.sync += output.seqn.eq(input.seqn)
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self.comb += [
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output.replace_occured.eq(0),
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output.nondata_replace_occured.eq(0)
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]
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self.comb += input.re.eq(input.payload.timestamp[glbl_fine_ts_width:] == self.coarse_timestamp)
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self.sync += output.valid.eq(input.re & input.readable)
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