mirror of https://github.com/m-labs/artiq.git
263 lines
9.5 KiB
Python
263 lines
9.5 KiB
Python
from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.cores.code_8b10b import Encoder, Decoder
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from microscope import *
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.gth_ultrascale_init import *
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class GTHSingle(Module):
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def __init__(self, refclk, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw, mode):
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assert (dw == 20) or (dw == 40)
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assert mode in ["master", "slave"]
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nwords = dw//10
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self.submodules.encoder = encoder = ClockDomainsRenamer("rtio_tx")(
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Encoder(nwords, True))
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self.submodules.decoders = decoders = [ClockDomainsRenamer("rtio_rx")(
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(Decoder(True))) for _ in range(nwords)]
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self.rx_ready = Signal()
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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# # #
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# TX generates RTIO clock, init must be in system domain
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tx_init = GTHInit(sys_clk_freq, False)
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# RX receives restart commands from RTIO domain
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rx_init = ClockDomainsRenamer("rtio_tx")(GTHInit(rtio_clk_freq, True))
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self.submodules += tx_init, rx_init
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cpll_lock = Signal()
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self.comb += [
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tx_init.plllock.eq(cpll_lock),
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rx_init.plllock.eq(cpll_lock)
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]
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txdata = Signal(dw)
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rxdata = Signal(dw)
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rxphaligndone = Signal()
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self.specials += \
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Instance("GTHE3_CHANNEL",
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# Reset modes
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i_GTRESETSEL=0,
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i_RESETOVRD=0,
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# PMA Attributes
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p_PMA_RSV1=0xf800,
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p_RX_BIAS_CFG0=0x0AB4,
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p_RX_CM_TRIM=0b1010,
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p_RX_CLK25_DIV=5,
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p_TX_CLK25_DIV=5,
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# Power-Down Attributes
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p_PD_TRANS_TIME_FROM_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x19,
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p_PD_TRANS_TIME_TO_P2=0x64,
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# CPLL
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p_CPLL_CFG0=0x67f8,
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p_CPLL_CFG1=0xa4ac,
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p_CPLL_CFG2=0xf007,
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p_CPLL_CFG3=0x0000,
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p_CPLL_FBDIV=5,
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p_CPLL_FBDIV_45=4,
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p_CPLL_REFCLK_DIV=1,
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p_RXOUT_DIV=2,
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p_TXOUT_DIV=2,
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i_CPLLRESET=0,
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i_CPLLPD=0,
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o_CPLLLOCK=cpll_lock,
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i_CPLLLOCKEN=1,
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i_CPLLREFCLKSEL=0b001,
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i_TSTIN=2**20-1,
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i_GTREFCLK0=refclk,
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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i_TXSYSCLKSEL=0b00,
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i_TXPLLCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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i_GTTXRESET=tx_init.gtXxreset,
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o_TXRESETDONE=tx_init.Xxresetdone,
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i_TXDLYSRESET=tx_init.Xxdlysreset,
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o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
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o_TXPHALIGNDONE=tx_init.Xxphaligndone,
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i_TXUSERRDY=tx_init.Xxuserrdy,
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i_TXSYNCMODE=1,
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# TX data
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p_TX_DATA_WIDTH=dw,
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p_TX_INT_DATAWIDTH=dw == 40,
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i_TXCTRL0=Cat(*[txdata[10*i+8] for i in range(nwords)]),
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i_TXCTRL1=Cat(*[txdata[10*i+9] for i in range(nwords)]),
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i_TXDATA=Cat(*[txdata[10*i:10*i+8] for i in range(nwords)]),
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i_TXUSRCLK=ClockSignal("rtio_tx"),
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i_TXUSRCLK2=ClockSignal("rtio_tx"),
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# TX electrical
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i_TXPD=0b00,
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p_TX_CLKMUX_EN=1,
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i_TXBUFDIFFCTRL=0b000,
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i_TXDIFFCTRL=0b1100,
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# RX Startup/Reset
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i_GTRXRESET=rx_init.gtXxreset,
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o_RXRESETDONE=rx_init.Xxresetdone,
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i_RXDLYSRESET=rx_init.Xxdlysreset,
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o_RXPHALIGNDONE=rxphaligndone,
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i_RXSYNCALLIN=rxphaligndone,
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i_RXUSERRDY=rx_init.Xxuserrdy,
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i_RXSYNCIN=0,
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i_RXSYNCMODE=1,
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o_RXSYNCDONE=rx_init.Xxsyncdone,
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# RX AFE
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i_RXDFEAGCCTRL=1,
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i_RXDFEXYDEN=1,
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i_RXLPMEN=1,
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i_RXOSINTCFG=0xd,
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i_RXOSINTEN=1,
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# RX clock
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i_RXRATE=0,
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i_RXDLYBYPASS=0,
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p_RXBUF_EN="FALSE",
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p_RX_XCLK_SEL="RXUSR",
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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i_RXPLLCLKSEL=0b00,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK2=ClockSignal("rtio_rx"),
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# RX Clock Correction Attributes
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p_CLK_CORRECT_USE="FALSE",
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p_CLK_COR_SEQ_1_1=0b0100000000,
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p_CLK_COR_SEQ_2_1=0b0100000000,
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p_CLK_COR_SEQ_1_ENABLE=0b1111,
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p_CLK_COR_SEQ_2_ENABLE=0b1111,
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# RX data
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p_RX_DATA_WIDTH=dw,
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p_RX_INT_DATAWIDTH=dw == 40,
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o_RXCTRL0=Cat(*[rxdata[10*i+8] for i in range(nwords)]),
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o_RXCTRL1=Cat(*[rxdata[10*i+9] for i in range(nwords)]),
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o_RXDATA=Cat(*[rxdata[10*i:10*i+8] for i in range(nwords)]),
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# RX electrical
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i_RXPD=0b00,
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p_RX_CLKMUX_EN=1,
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i_RXELECIDLEMODE=0b11,
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# Pads
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i_GTHRXP=rx_pads.p,
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i_GTHRXN=rx_pads.n,
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o_GTHTXP=tx_pads.p,
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o_GTHTXN=tx_pads.n
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)
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self.submodules += [
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add_probe_async("drtio_gth", "cpll_lock", cpll_lock),
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add_probe_async("drtio_gth", "txuserrdy", tx_init.Xxuserrdy),
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add_probe_async("drtio_gth", "tx_init_done", tx_init.done),
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add_probe_async("drtio_gth", "rxuserrdy", rx_init.Xxuserrdy),
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add_probe_async("drtio_gth", "rx_init_done", rx_init.done),
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add_probe_buffer("drtio_gth", "txdata", txdata, clock_domain="rtio_tx"),
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add_probe_buffer("drtio_gth", "rxdata", rxdata, clock_domain="rtio_rx")
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]
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# tx clocking
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tx_reset_deglitched = Signal()
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio_tx = ClockDomain()
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if mode == "master":
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self.specials += \
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Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk, i_DIV=0)
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self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
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# rx clocking
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rx_reset_deglitched = Signal()
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rx_reset_deglitched.attr.add("no_retiming")
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self.sync.rtio_tx += rx_reset_deglitched.eq(~rx_init.done)
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self.clock_domains.cd_rtio_rx = ClockDomain()
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self.specials += [
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Instance("BUFG_GT", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
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]
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# tx data
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self.comb += txdata.eq(Cat(*[encoder.output[i] for i in range(nwords)]))
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# rx data
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for i in range(nwords):
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self.comb += decoders[i].input.eq(rxdata[10*i:10*(i+1)])
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# clock alignment
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clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq)
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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rx_init.restart.eq(clock_aligner.restart),
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self.rx_ready.eq(clock_aligner.ready)
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]
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self.submodules += add_probe_async("drtio_gth", "clock_aligner_ready", clock_aligner.ready)
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class GTH(Module, TransceiverInterface):
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
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self.nchannels = nchannels = len(tx_pads)
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self.gths = []
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# # #
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refclk = Signal()
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self.specials += Instance("IBUFDS_GTE3",
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i_CEB=0,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk)
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rtio_tx_clk = Signal()
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channel_interfaces = []
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for i in range(nchannels):
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mode = "master" if i == master else "slave"
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gth = GTHSingle(refclk, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
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if mode == "master":
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self.comb += rtio_tx_clk.eq(gth.cd_rtio_tx.clk)
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else:
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self.comb += gth.cd_rtio_tx.clk.eq(rtio_tx_clk)
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self.gths.append(gth)
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setattr(self.submodules, "gth"+str(i), gth)
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channel_interface = ChannelInterface(gth.encoder, gth.decoders)
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self.comb += channel_interface.rx_ready.eq(gth.rx_ready)
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channel_interfaces.append(channel_interface)
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TransceiverInterface.__init__(self, channel_interfaces)
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self.comb += [
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self.cd_rtio.clk.eq(self.gths[master].cd_rtio_tx.clk),
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self.cd_rtio.rst.eq(reduce(or_, [gth.cd_rtio_tx.rst for gth in self.gths]))
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]
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for i in range(nchannels):
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self.comb += [
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getattr(self, "cd_rtio_rx" + str(i)).clk.eq(self.gths[i].cd_rtio_rx.clk),
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getattr(self, "cd_rtio_rx" + str(i)).rst.eq(self.gths[i].cd_rtio_rx.rst)
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]
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