mirror of https://github.com/m-labs/artiq.git
175 lines
6.2 KiB
Python
175 lines
6.2 KiB
Python
from artiq.language.core import (kernel, portable, delay_mu, delay)
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from artiq.language.units import ns, us
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from artiq.coredevice import spi
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# Designed from the data sheets and somewhat after the linux kernel
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# iio driver.
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_AD5360_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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_AD5360_CMD_DATA = 3 << 22
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_AD5360_CMD_OFFSET = 2 << 22
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_AD5360_CMD_GAIN = 1 << 22
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_AD5360_CMD_SPECIAL = 0 << 22
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@portable
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def _AD5360_WRITE_CHANNEL(c):
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return (c + 8) << 16
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_AD5360_SPECIAL_NOP = 0 << 16
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_AD5360_SPECIAL_CONTROL = 1 << 16
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_AD5360_SPECIAL_OFS0 = 2 << 16
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_AD5360_SPECIAL_OFS1 = 3 << 16
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_AD5360_SPECIAL_READ = 5 << 16
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@portable
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def _AD5360_READ_CHANNEL(ch):
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return (ch + 8) << 7
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_AD5360_READ_X1A = 0x000 << 7
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_AD5360_READ_X1B = 0x040 << 7
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_AD5360_READ_OFFSET = 0x080 << 7
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_AD5360_READ_GAIN = 0x0c0 << 7
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_AD5360_READ_CONTROL = 0x101 << 7
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_AD5360_READ_OFS0 = 0x102 << 7
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_AD5360_READ_OFS1 = 0x103 << 7
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class AD5360:
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"""
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Support for the Analog devices AD53[67][0123]
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multi-channel Digital to Analog Converters
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:param spi_device: Name of the SPI bus this device is on.
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:param ldac_device: Name of the TTL device that LDAC is connected to
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(optional). Needs to be explicitly initialized to high.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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"""
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def __init__(self, dmgr, spi_device, ldac_device=None, chip_select=1):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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if ldac_device is not None:
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self.ldac = dmgr.get(ldac_device)
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=4, read_div=7):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by the duration of two
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RTIO-to-Wishbone bus transactions.
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:param write_div: Write clock divider.
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:param read_div: Read clock divider.
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"""
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# write: 2*8ns >= 10ns = t_6 (clk falling to cs_n rising)
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# read: 4*8*ns >= 25ns = t_22 (clk falling to miso valid)
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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@kernel
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def write(self, data):
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"""Write 24 bits of data.
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This method advances the timeline by the duration of the SPI transfer
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and the required CS high time.
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"""
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self.bus.write(data << 8)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def write_offsets(self, value=0x1fff):
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"""Write the OFS0 and OFS1 offset DACs.
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This method advances the timeline by twice the duration of
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:meth:`write`.
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:param value: Value to set both offset registers to.
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"""
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value &= 0x3fff
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS0 | value)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS1 | value)
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@kernel
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def write_channel(self, channel=0, value=0, op=_AD5360_CMD_DATA):
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"""Write to a channel register.
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This method advances the timeline by the duration of :meth:`write`.
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:param channel: Channel number to write to.
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:param value: 16 bit value to write to the register.
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:param op: Operation to perform, one of :const:`_AD5360_CMD_DATA`,
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:const:`_AD5360_CMD_OFFSET`, :const:`_AD5360_CMD_GAIN`
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(default: :const:`_AD5360_CMD_DATA`).
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"""
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channel &= 0x3f
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value &= 0xffff
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self.write(op | _AD5360_WRITE_CHANNEL(channel) | value)
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@kernel
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def read_channel_sync(self, channel=0, op=_AD5360_READ_X1A):
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"""Read a channel register.
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This method advances the timeline by the duration of :meth:`write` plus
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three RTIO-to-Wishbone transactions.
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:param channel: Channel number to read from.
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:param op: Operation to perform, one of :const:`_AD5360_READ_X1A`,
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:const:`_AD5360_READ_X1B`, :const:`_AD5360_READ_OFFSET`,
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:const:`_AD5360_READ_GAIN` (default: :const:`_AD5360_READ_X1A`).
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:return: The 16 bit register value.
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"""
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channel &= 0x3f
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_READ | op |
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_AD5360_READ_CHANNEL(channel))
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self.bus.set_xfer(self.chip_select, 0, 24)
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self.write(_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_NOP)
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self.bus.read_async()
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self.bus.set_xfer(self.chip_select, 24, 0)
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return self.bus.input_async() & 0xffff
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@kernel
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def load(self):
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"""Pulse the LDAC line.
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This method advances the timeline by two RTIO clock periods (16 ns).
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"""
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self.ldac.off()
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# t13 = 10ns ldac pulse width low
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delay_mu(2*self.bus.ref_period_mu)
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self.ldac.on()
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@kernel
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def set(self, values, op=_AD5360_CMD_DATA):
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"""Write to several channels and pulse LDAC to update the channels.
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This method does not advance the timeline. Write events are scheduled
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in the past. The DACs will synchronously start changing their output
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levels `now`.
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:param values: List of 16 bit values to write to the channels.
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:param op: Operation to perform, one of :const:`_AD5360_CMD_DATA`,
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:const:`_AD5360_CMD_OFFSET`, :const:`_AD5360_CMD_GAIN`
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(default: :const:`_AD5360_CMD_DATA`).
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"""
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# compensate all delays that will be applied
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delay_mu(-len(values)*(self.bus.xfer_period_mu +
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self.bus.write_period_mu +
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self.bus.ref_period_mu) -
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3*self.bus.ref_period_mu -
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self.core.seconds_to_mu(1.5*us))
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for i in range(len(values)):
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self.write_channel(i, values[i], op)
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delay_mu(3*self.bus.ref_period_mu + # latency alignment ttl to spi
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self.core.seconds_to_mu(1.5*us)) # t10 max busy low for one channel
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self.load()
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delay_mu(-2*self.bus.ref_period_mu) # load(), t13
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