mirror of https://github.com/m-labs/artiq
56 lines
1.8 KiB
Python
56 lines
1.8 KiB
Python
"""
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Driver for the AD9912 DDS.
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"""
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from artiq.language.core import kernel, delay_mu
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from artiq.language.units import ns, us
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from artiq.coredevice import spi
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_AD9912_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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class AD9912:
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"""
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Support for the Analog devices AD9912 DDS
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:param spi_device: Name of the SPI bus this device is on.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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"""
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def __init__(self, dmgr, spi_device, chip_select):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=5, read_div=20):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by the duration of two
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RTIO-to-Wishbone bus transactions.
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:param write_div: Write clock divider.
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:param read_div: Read clock divider.
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"""
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# write: 5*8ns >= 40ns = t_clk (typ clk rate)
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# read: 2*8*ns >= 25ns = t_dv (clk falling to miso valid) + RTT
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self.bus.set_config_mu(_AD9912_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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@kernel
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def write(self, data):
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"""Write 24 bits of data.
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This method advances the timeline by the duration of the SPI transfer
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and the required CS high time.
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"""
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self.bus.write(data << 8)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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