mirror of https://github.com/m-labs/artiq.git
150 lines
4.7 KiB
Python
150 lines
4.7 KiB
Python
from migen import *
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from migen.genlib.io import *
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from migen.genlib.misc import BitSlip, WaitTimer
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from misoc.interconnect import stream
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from misoc.cores.code_8b10b import Encoder, Decoder
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from artiq.gateware.serwb.datapath import TXDatapath, RXDatapath
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class _KUSerdesClocking(Module):
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def __init__(self, pads, mode="master"):
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self.refclk = Signal()
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# # #
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# In Master mode, generate the linerate/10 clock. Slave will re-multiply it.
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if mode == "master":
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converter = stream.Converter(40, 8)
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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converter.sink.data.eq(Replicate(Signal(10, reset=0b1111100000), 4)),
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]
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self.specials += [
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Instance("OSERDESE3",
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p_DATA_WIDTH=8, p_INIT=0,
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p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0,
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p_IS_RST_INVERTED=0,
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o_OQ=self.refclk,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
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i_D=converter.source.data
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),
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DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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]
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# In Slave mode, multiply the clock provided by Master with a PLL/MMCM
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elif mode == "slave":
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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class _KUSerdesTX(Module):
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def __init__(self, pads):
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# Control
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.sink = sink = stream.Endpoint([("data", 32)])
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# # #
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# Datapath
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self.submodules.datapath = datapath = TXDatapath(8)
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self.comb += [
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sink.connect(datapath.sink),
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datapath.source.ack.eq(1),
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datapath.idle.eq(idle),
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datapath.comma.eq(comma)
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]
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# Output Data(DDR with sys4x)
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data = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_DATA_WIDTH=8, p_INIT=0,
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p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
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o_OQ=data,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
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i_D=datapath.source.data
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),
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DifferentialOutput(data, pads.tx_p, pads.tx_n)
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]
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class _KUSerdesRX(Module):
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def __init__(self, pads):
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# Control
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self.delay_rst = Signal()
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self.delay_inc = Signal()
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self.bitslip_value = bitslip_value = Signal(6)
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# Status
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.source = source = stream.Endpoint([("data", 32)])
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# # #
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# Data input (DDR with sys4x)
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data_nodelay = Signal()
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data_delayed = Signal()
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data_deserialized = Signal(8)
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self.specials += [
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DifferentialInput(pads.rx_p, pads.rx_n, data_nodelay),
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Instance("IDELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0,
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p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
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p_DELAY_FORMAT="COUNT", p_DELAY_SRC="IDATAIN",
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p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
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i_CLK=ClockSignal("sys"),
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i_RST=self.delay_rst, i_LOAD=0,
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i_INC=1, i_EN_VTC=0,
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i_CE=self.delay_inc,
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i_IDATAIN=data_nodelay, o_DATAOUT=data_delayed
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),
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Instance("ISERDESE3",
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p_IS_CLK_INVERTED=0,
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p_IS_CLK_B_INVERTED=1,
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p_DATA_WIDTH=8,
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i_D=data_delayed,
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i_RST=ResetSignal("sys"),
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i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("sys4x"),
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i_CLK_B=ClockSignal("sys4x"), # locally inverted
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i_CLKDIV=ClockSignal("sys"),
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o_Q=data_deserialized
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)
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]
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# Datapath
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self.submodules.datapath = datapath = RXDatapath(8)
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self.comb += [
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datapath.sink.stb.eq(1),
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datapath.sink.data.eq(data_deserialized),
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datapath.bitslip_value.eq(bitslip_value),
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datapath.source.connect(source),
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idle.eq(datapath.idle),
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comma.eq(datapath.comma)
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]
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@ResetInserter()
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class KUSerdes(Module):
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def __init__(self, pads, mode="master"):
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self.submodules.clocking = _KUSerdesClocking(pads, mode)
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self.submodules.tx = _KUSerdesTX(pads)
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self.submodules.rx = _KUSerdesRX(pads)
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