mirror of https://github.com/m-labs/artiq.git
204 lines
7.5 KiB
ReStructuredText
204 lines
7.5 KiB
ReStructuredText
Installing ARTIQ
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================
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Preparing the core device FPGA board
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------------------------------------
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These steps are required to generate bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
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* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* The Pipistrello is supported by Webpack, the KC705 is not.
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* During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
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* Create a development directory: ::
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$ mkdir ~/artiq-dev
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* Install Migen: ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/migen
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$ cd ~/artiq-dev/migen
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$ python3 setup.py develop --user
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.. note::
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The options ``develop`` and ``--user`` are for setup.py to install Migen in ``~/.local/lib/python3.4``.
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* Install OpenRISC GCC/binutils toolchain (or1k-elf-...): ::
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$ mkdir ~/artiq-dev
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$ cd ~/artiq-dev
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$ git clone https://github.com/openrisc/or1k-src
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$ mkdir ~/artiq-dev/or1k-src/build
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$ cd ~/artiq-dev/or1k-src/build
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$ ../configure --target=or1k-elf --enable-shared --disable-itcl \
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--disable-tk --disable-tcl --disable-winsup \
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--disable-gdbtk --disable-libgui --disable-rda \
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--disable-sid --disable-sim --disable-gdb \
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--disable-newlib --disable-libgloss --disable-werror
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$ make -j4
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$ sudo make install
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$ cd ~/artiq-dev
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$ git clone https://github.com/openrisc/or1k-gcc
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$ mkdir ~/artiq-dev/or1k-gcc/build
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$ cd ~/artiq-dev/or1k-gcc/build
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$ ../configure --target=or1k-elf --enable-languages=c \
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--disable-shared --disable-libssp
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$ make -j4
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$ sudo make install
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* Install JTAG tools needed to program the Pipistrello and KC705:
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::
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$ cd ~/artiq-dev
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$ svn co https://xc3sprog.svn.sourceforge.net/svnroot/xc3sprog/trunk xc3sprog
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$ cd ~/artiq-dev/xc3sprog
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$ cmake . && make
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$ sudo make install
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.. note::
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It is safe to ignore the message "Could NOT find LIBFTD2XX" (libftd2xx is different from libftdi, and is not required).
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* Install the required flash proxy bitstreams:
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The purpose of the flash proxy bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
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* Pipistrello:
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::
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$ cd ~/artiq-dev
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$ wget http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
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Then copy ``~/artiq-dev/bscan_spi_lx45_csg324.bit`` to ``~/.migen``, ``/usr/local/share/migen`` or ``/usr/share/migen``.
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* KC705:
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::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/bscan_spi_kc705
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Build the bitstream and copy it to one of the folders above.
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* Download MiSoC: ::
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$ cd ~/artiq-dev
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$ git clone --recursive https://github.com/m-labs/misoc
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$ export MSCDIR=~/artiq-dev/misoc # append this line to .bashrc
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* Download and install ARTIQ: ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/artiq
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$ python3 setup.py develop --user
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* Build and flash the bitstream and BIOS by running `from the MiSoC top-level directory`: ::
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$ cd ~/artiq-dev/misoc
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$ ./make.py -X ~/artiq-dev/artiq/soc -t artiq_ppro all
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* Then, build and flash the ARTIQ runtime: ::
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$ cd ~/artiq-dev/artiq/soc/runtime && make runtime.fbi
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$ ~/artiq-dev/artiq/artiq/frontend/artiq_flash.sh -t pipistrello -d $PWD -r
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.. note:: The `-t` option specifies the board your are targeting. Available options are ``kc705`` and ``pipistrello``.
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the bitstream that was newly written into the flash): ::
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$ make -C ~/artiq-dev/misoc/tools # do only once
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$ ~/artiq-dev/misoc/tools/flterm --port /dev/ttyUSB1
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MiSoC BIOS http://m-labs.hk
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[...]
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Booting from flash...
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Loading xxxxx bytes from flash...
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Executing booted program.
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ARTIQ runtime built <date/time>
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The communication parameters are 115200 8-N-1.
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Installing the host-side software
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---------------------------------
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* Install LLVM and the llvmlite Python bindings: ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/openrisc/llvm-or1k
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$ cd ~/artiq-dev/llvm-or1k/tools
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$ git clone https://github.com/openrisc/clang-or1k clang
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$ cd ~/artiq-dev/llvm-or1k
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$ mkdir build
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$ cd ~/artiq-dev/llvm-or1k/build
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$ cmake .. -DCMAKE_INSTALL_PREFIX=/usr/local/llvm-or1k -DLLVM_TARGETS_TO_BUILD=OR1K -DCMAKE_BUILD_TYPE=Debug -DBUILD_SHARED_LIBS=ON
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$ make -j4
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$ sudo make install
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$ cd ~/artiq-dev
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$ git clone https://github.com/numba/llvmlite
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$ cd ~/artiq-dev/llvmlite
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$ patch -p1 < ~/artiq-dev/artiq/misc/llvmlite-add-all-targets.patch
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$ PATH=/usr/local/llvm-or1k/bin:$PATH sudo -E python3 setup.py install
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.. note::
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llvmlite is in development and its API is not stable yet. Commit ID ``11a8303d02e3d6dd2d1e0e9065701795cd8a979f`` is known to work.
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.. note::
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Compilation of LLVM can take more than 30 min on some machines.
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* Install ARTIQ (without the GUI): ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/artiq # if not already done
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$ cd artiq
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$ python3 setup.py develop --user
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* Install ARTIQ (with the GUI): ::
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$ cd ~/artiq-dev
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$ git clone https://github.com/m-labs/cairoplot3
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$ cd cairoplot3
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$ python3 setup.py install --user
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$ cd -
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$ git clone https://github.com/m-labs/gbulb
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$ cd gbulb
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$ python3 setup.py install --user
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$ cd -
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$ git clone https://github.com/m-labs/artiq # if not already done
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$ cd artiq
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$ ARTIQ_GUI=1 python3 setup.py develop --user
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.. note::
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Use ARTIQ_GUI=1 to install GUI dependencies which are only supported on Linux for now, to install ARTIQ on Windows do not set ARTIQ_GUI.
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* Build the documentation: ::
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$ cd ~/artiq-dev/artiq/doc/manual
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$ make html
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Ubuntu 14.04 specific instructions
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----------------------------------
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This command installs all the required packages: ::
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$ sudo apt-get install build-essential autotools-dev file git patch perl xutils-devs python3-pip texinfo flex bison libmpc-dev python3-serial python3-dateutil python3-prettytable python3-setuptools python3-numpy python3-scipy python3-sphinx python3-h5py python3-gi python3-dev python-dev subversion cmake libusb-dev libftdi-dev pkg-config
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Note that ARTIQ requires Python 3.4 or above.
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To set user permissions on the JTAG and serial ports of the Pipistrello, create a ``/etc/udev/rules.d/30-usb-papilio.rules`` file containing the following: ::
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SUBSYSTEM=="usb", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", GROUP="dialout"
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Then reload ``udev``, add your user to the ``dialout`` group, and log out and log in again: ::
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$ sudo invoke-rc.d udev reload
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$ sudo adduser <your username> dialout
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$ logout
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