mirror of https://github.com/m-labs/artiq
966 lines
37 KiB
Python
Executable File
966 lines
37 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialOutput
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores.a7_gtp import *
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from misoc.targets.kasli import (
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BaseSoC, MiniSoC, soc_kasli_args, soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
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from artiq.gateware import eem
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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clk_synth = platform.request("si5324_clkout_fabric")
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clk_synth_se = Signal()
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clk_synth_buffered = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_buffered),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=clk_synth_buffered,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0)))
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self.csr_devices.append("leds")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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class Opticlock(_StandaloneBase):
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"""
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Opticlock extension variant configuration
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.0"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Novogorny.add_std(self, 3, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class SUServo(_StandaloneBase):
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"""
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SUServo (Sampler-Urukul-Servo) extension variant configuration
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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# EEM0, EEM1: DIO
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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# EEM3/2: Sampler, EEM5/4: Urukul, EEM7/6: Urukul
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eem.SUServo.add_std(
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self, eems_sampler=(3, 2),
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eems_urukul0=(5, 4), eems_urukul1=(7, 6))
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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pads = self.platform.lookup_request("sampler3_adc_data_p")
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self.platform.add_false_path_constraints(
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pads.clkout, self.rtio_crg.cd_rtio.clk)
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self.platform.add_false_path_constraints(
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pads.clkout, self.crg.cd_sys.clk)
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class SYSU(_StandaloneBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.0"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
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eem.DIO.add_std(self, 3,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
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for i in range(4, 7):
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eem.DIO.add_std(self, i,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class MITLL(_StandaloneBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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self.grabber_csr_group = []
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eem.DIO.add_std(self, 4,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
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eem.Urukul.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 5, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 6, ttl_serdes_7series.Output_8X)
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eem.Grabber.add_std(self, 1, 0)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
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class USTC(_StandaloneBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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self.grabber_csr_group = []
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eem.DIO.add_std(self, 5,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 6,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 7,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 2, 1, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 4, 3, ttl_serdes_7series.Output_8X)
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eem.Grabber.add_std(self, 0)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
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class Tsinghua(_StandaloneBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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self.grabber_csr_group = []
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eem.DIO.add_std(self, 4,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 6, 5, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
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eem.Grabber.add_std(self, 1, 0)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
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class WIPM(_StandaloneBase):
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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|
self.comb += self.platform.request("clk_sel").eq(1)
|
|
|
|
self.rtio_channels = []
|
|
eem.DIO.add_std(self, 4,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
|
|
eem.Sampler.add_std(self, 6, 5, ttl_serdes_7series.Output_8X)
|
|
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
|
|
|
|
for i in (1, 2):
|
|
sfp_ctl = self.platform.request("sfp_ctl", i)
|
|
phy = ttl_simple.Output(sfp_ctl.led)
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
class PTB(_StandaloneBase):
|
|
"""PTB Kasli variant
|
|
|
|
F.k.a. ptb-schmidt, ptb-mehlstaeubler, ptb-huntemann-11, ptb-huntemann-19,
|
|
and ufr-warring in the artiq-setup repository
|
|
"""
|
|
def __init__(self, hw_rev=None, **kwargs):
|
|
if hw_rev is None:
|
|
hw_rev = "v1.1"
|
|
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
|
|
|
self.config["SI5324_AS_SYNTHESIZER"] = None
|
|
# self.config["SI5324_EXT_REF"] = None
|
|
self.config["RTIO_FREQUENCY"] = "125.0"
|
|
if hw_rev == "v1.0":
|
|
# EEM clock fan-out from Si5324, not MMCX
|
|
self.comb += self.platform.request("clk_sel").eq(1)
|
|
|
|
self.rtio_channels = []
|
|
eem.DIO.add_std(self, 0,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.DIO.add_std(self, 1,
|
|
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
|
|
eem.DIO.add_std(self, 2,
|
|
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
|
|
|
|
for i in (1, 2):
|
|
sfp_ctl = self.platform.request("sfp_ctl", i)
|
|
phy = ttl_simple.Output(sfp_ctl.led)
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
class HUB(_StandaloneBase):
|
|
"""HUB Kasli variant
|
|
|
|
F.k.a. hub-krutzik, luh-ospelkaus-13, and luh-ospelkaus-14
|
|
in the artiq-setup repository
|
|
"""
|
|
def __init__(self, hw_rev=None, **kwargs):
|
|
if hw_rev is None:
|
|
hw_rev = "v1.1"
|
|
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
|
|
|
self.config["SI5324_AS_SYNTHESIZER"] = None
|
|
# self.config["SI5324_EXT_REF"] = None
|
|
self.config["RTIO_FREQUENCY"] = "125.0"
|
|
if hw_rev == "v1.0":
|
|
# EEM clock fan-out from Si5324, not MMCX
|
|
self.comb += self.platform.request("clk_sel").eq(1)
|
|
|
|
self.rtio_channels = []
|
|
eem.DIO.add_std(self, 0,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.DIO.add_std(self, 1,
|
|
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
|
|
eem.DIO.add_std(self, 2,
|
|
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 4, None, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 5, None, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
|
|
|
|
for i in (1, 2):
|
|
sfp_ctl = self.platform.request("sfp_ctl", i)
|
|
phy = ttl_simple.Output(sfp_ctl.led)
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
class LUH(_StandaloneBase):
|
|
"""LUH Kasli variant
|
|
|
|
F.k.a. luh-ospelkaus-16, luh-ospelkaus-18 in the artiq-setup repository
|
|
"""
|
|
def __init__(self, hw_rev=None, **kwargs):
|
|
if hw_rev is None:
|
|
hw_rev = "v1.1"
|
|
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
|
|
|
self.config["SI5324_AS_SYNTHESIZER"] = None
|
|
# self.config["SI5324_EXT_REF"] = None
|
|
self.config["RTIO_FREQUENCY"] = "125.0"
|
|
if hw_rev == "v1.0":
|
|
# EEM clock fan-out from Si5324, not MMCX
|
|
self.comb += self.platform.request("clk_sel").eq(1)
|
|
|
|
self.rtio_channels = []
|
|
self.grabber_csr_group = []
|
|
eem.DIO.add_std(self, 0,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.DIO.add_std(self, 1,
|
|
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
|
|
eem.DIO.add_std(self, 2,
|
|
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 4, None, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 5, None, ttl_serdes_7series.Output_8X)
|
|
eem.Grabber.add_std(self, 6)
|
|
|
|
for i in (1, 2):
|
|
sfp_ctl = self.platform.request("sfp_ctl", i)
|
|
phy = ttl_simple.Output(sfp_ctl.led)
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
self.config["HAS_GRABBER"] = None
|
|
self.add_csr_group("grabber", self.grabber_csr_group)
|
|
self.platform.add_false_path_constraints(
|
|
self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
|
|
|
|
|
|
class Tester(_StandaloneBase):
|
|
"""
|
|
Configuration for CI tests. Contains the maximum number of different EEMs.
|
|
"""
|
|
def __init__(self, hw_rev=None, **kwargs):
|
|
if hw_rev is None:
|
|
hw_rev = "v1.1"
|
|
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
|
|
|
self.config["SI5324_AS_SYNTHESIZER"] = None
|
|
# self.config["SI5324_EXT_REF"] = None
|
|
self.config["RTIO_FREQUENCY"] = "125.0"
|
|
if hw_rev == "v1.0":
|
|
# EEM clock fan-out from Si5324, not MMCX
|
|
self.comb += self.platform.request("clk_sel").eq(1)
|
|
|
|
self.rtio_channels = []
|
|
eem.DIO.add_std(self, 5,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)
|
|
eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
|
|
eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
|
|
|
|
for i in (1, 2):
|
|
sfp_ctl = self.platform.request("sfp_ctl", i)
|
|
phy = ttl_simple.Output(sfp_ctl.led)
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
class _RTIOClockMultiplier(Module):
|
|
def __init__(self, rtio_clk_freq):
|
|
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
|
|
|
|
# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
|
|
clkfbout = Signal()
|
|
clkfbin = Signal()
|
|
rtiox4_clk = Signal()
|
|
self.specials += [
|
|
Instance("MMCME2_BASE",
|
|
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
|
|
i_CLKIN1=ClockSignal("rtio"),
|
|
i_RST=ResetSignal("rtio"),
|
|
|
|
p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
|
|
|
|
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
|
|
|
|
p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
|
|
),
|
|
Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
|
|
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk)
|
|
]
|
|
|
|
|
|
class _MasterBase(MiniSoC, AMPSoC):
|
|
mem_map = {
|
|
"cri_con": 0x10000000,
|
|
"rtio": 0x20000000,
|
|
"rtio_dma": 0x30000000,
|
|
"drtioaux": 0x50000000,
|
|
"mailbox": 0x70000000
|
|
}
|
|
mem_map.update(MiniSoC.mem_map)
|
|
|
|
def __init__(self, **kwargs):
|
|
MiniSoC.__init__(self,
|
|
cpu_type="or1k",
|
|
sdram_controller_type="minicon",
|
|
l2_size=128*1024,
|
|
ethmac_nrxslots=4,
|
|
ethmac_ntxslots=4,
|
|
**kwargs)
|
|
AMPSoC.__init__(self)
|
|
add_identifier(self)
|
|
|
|
platform = self.platform
|
|
rtio_clk_freq = 150e6
|
|
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
self.config["HAS_SI5324"] = None
|
|
self.config["SI5324_SOFT_RESET"] = None
|
|
self.config["SI5324_AS_SYNTHESIZER"] = None
|
|
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
|
|
|
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)]
|
|
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
|
|
self.submodules.drtio_transceiver = gtp_7series.GTP(
|
|
qpll_channel=self.drtio_qpll_channel,
|
|
data_pads=[platform.request("sfp", i) for i in range(1, 3)],
|
|
sys_clk_freq=self.clk_freq,
|
|
rtio_clk_freq=rtio_clk_freq)
|
|
self.csr_devices.append("drtio_transceiver")
|
|
self.sync += self.disable_si5324_ibuf.eq(
|
|
~self.drtio_transceiver.stable_clkin.storage)
|
|
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
|
|
for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
|
|
|
|
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
|
|
|
drtio_csr_group = []
|
|
drtioaux_csr_group = []
|
|
drtioaux_memory_group = []
|
|
self.drtio_cri = []
|
|
for i in range(2):
|
|
core_name = "drtio" + str(i)
|
|
coreaux_name = "drtioaux" + str(i)
|
|
memory_name = "drtioaux" + str(i) + "_mem"
|
|
drtio_csr_group.append(core_name)
|
|
drtioaux_csr_group.append(coreaux_name)
|
|
drtioaux_memory_group.append(memory_name)
|
|
|
|
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
|
|
|
core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
|
setattr(self.submodules, core_name, core)
|
|
self.drtio_cri.append(core.cri)
|
|
self.csr_devices.append(core_name)
|
|
|
|
coreaux = cdr(DRTIOAuxController(core.link_layer))
|
|
setattr(self.submodules, coreaux_name, coreaux)
|
|
self.csr_devices.append(coreaux_name)
|
|
|
|
memory_address = self.mem_map["drtioaux"] + 0x800*i
|
|
self.add_wb_slave(memory_address, 0x800,
|
|
coreaux.bus)
|
|
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.config["HAS_DRTIO_ROUTING"] = None
|
|
self.add_csr_group("drtio", drtio_csr_group)
|
|
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
gtp = self.drtio_transceiver.gtps[0]
|
|
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
|
|
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gtp.txoutclk, gtp.rxoutclk)
|
|
for gtp in self.drtio_transceiver.gtps[1:]:
|
|
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, gtp.rxoutclk)
|
|
|
|
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
|
|
fix_serdes_timing_path(platform)
|
|
|
|
def add_rtio(self, rtio_channels):
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
|
|
self.csr_devices.append("rtio_core")
|
|
|
|
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
|
|
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
|
rtio.DMA(self.get_native_sdram_if()))
|
|
self.register_kernel_cpu_csrdevice("rtio")
|
|
self.register_kernel_cpu_csrdevice("rtio_dma")
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.rtio.cri, self.rtio_dma.cri],
|
|
[self.rtio_core.cri] + self.drtio_cri,
|
|
enable_routing=True)
|
|
self.register_kernel_cpu_csrdevice("cri_con")
|
|
|
|
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
|
|
self.get_native_sdram_if())
|
|
self.csr_devices.append("rtio_analyzer")
|
|
|
|
# Never running out of stupid features, GTs on A7 make you pack
|
|
# unrelated transceiver PLLs into one GTPE2_COMMON yourself.
|
|
def create_qpll(self):
|
|
# The GTP acts up if you send any glitch to its
|
|
# clock input, even while the PLL is held in reset.
|
|
self.disable_si5324_ibuf = Signal(reset=1)
|
|
self.disable_si5324_ibuf.attr.add("no_retiming")
|
|
si5324_clkout = self.platform.request("si5324_clkout")
|
|
si5324_clkout_buf = Signal()
|
|
self.specials += Instance("IBUFDS_GTE2",
|
|
i_CEB=self.disable_si5324_ibuf,
|
|
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
|
|
o_O=si5324_clkout_buf)
|
|
# Note precisely the rules Xilinx made up:
|
|
# refclksel=0b001 GTREFCLK0 selected
|
|
# refclksel=0b010 GTREFCLK1 selected
|
|
# but if only one clock is used, then it must be 001.
|
|
qpll_drtio_settings = QPLLSettings(
|
|
refclksel=0b001,
|
|
fbdiv=4,
|
|
fbdiv_45=5,
|
|
refclk_div=1)
|
|
qpll_eth_settings = QPLLSettings(
|
|
refclksel=0b010,
|
|
fbdiv=4,
|
|
fbdiv_45=5,
|
|
refclk_div=1)
|
|
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings,
|
|
self.crg.clk125_buf, qpll_eth_settings)
|
|
self.submodules += qpll
|
|
self.drtio_qpll_channel, self.ethphy_qpll_channel = qpll.channels
|
|
|
|
|
|
class _SatelliteBase(BaseSoC):
|
|
mem_map = {
|
|
"drtioaux": 0x50000000,
|
|
}
|
|
mem_map.update(BaseSoC.mem_map)
|
|
|
|
def __init__(self, **kwargs):
|
|
BaseSoC.__init__(self,
|
|
cpu_type="or1k",
|
|
sdram_controller_type="minicon",
|
|
l2_size=128*1024,
|
|
**kwargs)
|
|
add_identifier(self)
|
|
|
|
platform = self.platform
|
|
rtio_clk_freq = 150e6
|
|
|
|
disable_si5324_ibuf = Signal(reset=1)
|
|
disable_si5324_ibuf.attr.add("no_retiming")
|
|
si5324_clkout = platform.request("si5324_clkout")
|
|
si5324_clkout_buf = Signal()
|
|
self.specials += Instance("IBUFDS_GTE2",
|
|
i_CEB=disable_si5324_ibuf,
|
|
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
|
|
o_O=si5324_clkout_buf)
|
|
qpll_drtio_settings = QPLLSettings(
|
|
refclksel=0b001,
|
|
fbdiv=4,
|
|
fbdiv_45=5,
|
|
refclk_div=1)
|
|
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
|
|
self.submodules += qpll
|
|
|
|
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
|
|
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
|
|
self.submodules.drtio_transceiver = gtp_7series.GTP(
|
|
qpll_channel=qpll.channels[0],
|
|
data_pads=[platform.request("sfp", i) for i in range(3)],
|
|
sys_clk_freq=self.clk_freq,
|
|
rtio_clk_freq=rtio_clk_freq)
|
|
self.csr_devices.append("drtio_transceiver")
|
|
self.sync += disable_si5324_ibuf.eq(
|
|
~self.drtio_transceiver.stable_clkin.storage)
|
|
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
|
|
for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
|
|
|
|
self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
|
|
|
|
drtioaux_csr_group = []
|
|
drtioaux_memory_group = []
|
|
drtiorep_csr_group = []
|
|
self.drtio_cri = []
|
|
for i in range(3):
|
|
coreaux_name = "drtioaux" + str(i)
|
|
memory_name = "drtioaux" + str(i) + "_mem"
|
|
drtioaux_csr_group.append(coreaux_name)
|
|
drtioaux_memory_group.append(memory_name)
|
|
|
|
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
|
|
|
if i == 0:
|
|
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
|
|
core = cdr(DRTIOSatellite(
|
|
self.rtio_tsc, self.drtio_transceiver.channels[i],
|
|
self.rx_synchronizer))
|
|
self.submodules.drtiosat = core
|
|
self.csr_devices.append("drtiosat")
|
|
else:
|
|
corerep_name = "drtiorep" + str(i-1)
|
|
drtiorep_csr_group.append(corerep_name)
|
|
|
|
core = cdr(DRTIORepeater(
|
|
self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
|
setattr(self.submodules, corerep_name, core)
|
|
self.drtio_cri.append(core.cri)
|
|
self.csr_devices.append(corerep_name)
|
|
|
|
coreaux = cdr(DRTIOAuxController(core.link_layer))
|
|
setattr(self.submodules, coreaux_name, coreaux)
|
|
self.csr_devices.append(coreaux_name)
|
|
|
|
memory_address = self.mem_map["drtioaux"] + 0x800*i
|
|
self.add_wb_slave(memory_address, 0x800,
|
|
coreaux.bus)
|
|
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.config["HAS_DRTIO_ROUTING"] = None
|
|
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
|
self.add_csr_group("drtiorep", drtiorep_csr_group)
|
|
|
|
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
|
self.submodules.siphaser = SiPhaser7Series(
|
|
si5324_clkin=platform.request("si5324_clkin"),
|
|
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"),
|
|
ref_clk=self.crg.clk125_div2, ref_div2=True)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
|
self.csr_devices.append("siphaser")
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
self.config["HAS_SI5324"] = None
|
|
self.config["SI5324_SOFT_RESET"] = None
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
gtp = self.drtio_transceiver.gtps[0]
|
|
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
|
|
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gtp.txoutclk, gtp.rxoutclk)
|
|
for gtp in self.drtio_transceiver.gtps[1:]:
|
|
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, gtp.rxoutclk)
|
|
|
|
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
|
|
fix_serdes_timing_path(platform)
|
|
|
|
def add_rtio(self, rtio_channels):
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
|
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.drtiosat.cri],
|
|
[self.local_io.cri] + self.drtio_cri,
|
|
mode="sync", enable_routing=True)
|
|
|
|
|
|
class Master(_MasterBase):
|
|
def __init__(self, *args, **kwargs):
|
|
_MasterBase.__init__(self, *args, **kwargs)
|
|
|
|
self.rtio_channels = []
|
|
|
|
phy = ttl_simple.Output(self.platform.request("user_led", 0))
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
# matches Tester EEM numbers
|
|
eem.DIO.add_std(self, 5,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
class Satellite(_SatelliteBase):
|
|
def __init__(self, *args, **kwargs):
|
|
_SatelliteBase.__init__(self, *args, **kwargs)
|
|
|
|
self.rtio_channels = []
|
|
phy = ttl_simple.Output(self.platform.request("user_led", 0))
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
# matches Tester EEM numbers
|
|
eem.DIO.add_std(self, 5,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="ARTIQ device binary builder for Kasli systems")
|
|
builder_args(parser)
|
|
soc_kasli_args(parser)
|
|
parser.set_defaults(output_dir="artiq_kasli")
|
|
variants = {cls.__name__.lower(): cls for cls in [
|
|
Opticlock, SUServo, SYSU, MITLL, USTC, Tsinghua, WIPM, PTB, HUB, LUH,
|
|
Tester, Master, Satellite]}
|
|
parser.add_argument("-V", "--variant", default="opticlock",
|
|
help="variant: {} (default: %(default)s)".format(
|
|
"/".join(sorted(variants.keys()))))
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
try:
|
|
cls = variants[variant]
|
|
except KeyError:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
|
|
soc = cls(**soc_kasli_argdict(args))
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|