mirror of https://github.com/m-labs/artiq.git
177 lines
6.1 KiB
Python
177 lines
6.1 KiB
Python
from numpy import int32, int64
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from artiq.language.core import kernel, delay, portable
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from artiq.language.units import us, ns
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from artiq.coredevice.ad9912_reg import *
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import urukul
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class AD9912:
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"""
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AD9912 DDS channel on Urukul
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This class supports a single DDS channel and exposes the DDS,
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the digital step attenuator, and the RF switch.
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:param chip_select: Chip select configuration. On Urukul this is an
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encoded chip select and not "one-hot".
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:param cpld_device: Name of the Urukul CPLD this device is on.
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:param sw_device: Name of the RF switch device. The RF switch is a
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TTLOut channel available as the :attr:`sw` attribute of this instance.
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:param pll_n: DDS PLL multiplier. The DDS sample clock is
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f_ref*pll_n where f_ref is the reference frequency (set in the parent
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Urukul CPLD instance).
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus", "sw",
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"ftw_per_hz", "sysclk", "pll_n"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=10):
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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assert 4 <= chip_select <= 7
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.pll_n = pll_n
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self.sysclk = self.cpld.refclk*pll_n
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assert self.sysclk <= 1e9
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self.ftw_per_hz = 1/self.sysclk*(int64(1) << 48)
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@kernel
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def write(self, addr, data, length):
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"""Variable length write to a register.
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Up to 4 bytes.
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:param addr: Register address
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:param data: Data to be written: int32
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:param length: Length in bytes (1-4)
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"""
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assert length > 0
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assert length <= 4
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self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | ((length - 1) << 13)) << 16)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, length*8,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data << (32 - length*8))
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@kernel
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def read(self, addr, length):
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"""Variable length read from a register.
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Up to 4 bytes.
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:param addr: Register address
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:param length: Length in bytes (1-4)
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:return: Data read
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"""
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assert length > 0
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assert length <= 4
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self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END
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| spi.SPI_INPUT, length*8,
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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data = self.bus.read()
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if length < 4:
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data &= (1 << (length*8)) - 1
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return data
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@kernel
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def init(self):
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"""Initialize and configure the DDS.
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Sets up SPI mode, confirms chip presence, powers down unused blocks,
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and configures the PLL. Does not wait for PLL lock. Uses the
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IO_UPDATE signal multiple times.
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"""
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# SPI mode
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self.write(AD9912_SER_CONF, 0x99, length=1)
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self.cpld.io_update.pulse(1*us)
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# Verify chip ID and presence
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prodid = self.read(AD9912_PRODIDH, length=2)
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if (prodid != 0x1982) and (prodid != 0x1902):
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raise ValueError("Urukul AD9912 product id mismatch")
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delay(30*us)
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# HSTL power down, CMOS power down
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self.write(AD9912_PWRCNTRL1, 0x80, length=1)
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self.cpld.io_update.pulse(1*us)
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self.write(AD9912_N_DIV, self.pll_n//2 - 2, length=1)
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self.cpld.io_update.pulse(1*us)
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# I_cp = 375 µA, VCO high range
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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self.cpld.io_update.pulse(1*us)
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@kernel
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def set_att_mu(self, att):
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"""Set digital step attenuator in machine units.
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.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.set_att_mu`
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:param att: Attenuation setting, 8 bit digital.
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"""
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self.cpld.set_att_mu(self.chip_select - 4, att)
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@kernel
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def set_att(self, att):
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"""Set digital step attenuator in SI units.
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.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.set_att`
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:param att: Attenuation in dB. Higher values mean more attenuation.
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"""
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self.cpld.set_att(self.chip_select - 4, att)
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@kernel
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def set_mu(self, ftw, pow):
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"""Set profile 0 data in machine units.
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After the SPI transfer, the shared IO update pin is pulsed to
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activate the data.
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:param ftw: Frequency tuning word: 32 bit unsigned.
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:param pow: Phase tuning word: 16 bit unsigned.
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"""
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# streaming transfer of FTW and POW
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self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((AD9912_POW1 << 16) | (3 << 29))
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((pow << 16) | (int32(ftw >> 32) & 0xffff))
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(int32(ftw))
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self.cpld.io_update.pulse(10*ns)
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return int64(round(self.ftw_per_hz*frequency))
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@portable(flags={"fast-math"})
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def turns_to_pow(self, phase):
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"""Returns the phase offset word corresponding to the given
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phase.
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"""
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return int32(round((1 << 16)*phase))
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@kernel
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def set(self, frequency, phase=0.0):
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"""Set profile 0 data in SI units.
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.. seealso:: :meth:`set_mu`
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:param ftw: Frequency in Hz
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:param pow: Phase tuning word in turns
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"""
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self.set_mu(self.frequency_to_ftw(frequency),
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self.turns_to_pow(phase))
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