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Robert Jordens
324660ab40
Assume that rt2wb transactions either collide and are then reported (https://github.com/m-labs/artiq/issues/308) or that they complete and the delay with which they complete does not matter. If a transaction is ack'ed with a delay because the WB core's downstream logic is busy, that may lead to a later collision with another WB transaction.
13 lines
641 B
Python
13 lines
641 B
Python
from artiq.coredevice import exceptions, dds, spi
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from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,
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RTIOCollisionError, RTIOOverflow,
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DDSBatchError, CacheError)
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from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
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PHASE_MODE_TRACKING)
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__all__ = []
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__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollisionError",
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"RTIOOverflow", "DDSBatchError", "CacheError"]
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__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
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"PHASE_MODE_TRACKING"]
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