mirror of
https://github.com/m-labs/artiq.git
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212 lines
8.5 KiB
Python
212 lines
8.5 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from mibuild.xilinx.ise import XilinxISEToolchain
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.kc705 import MiniSoC
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from artiq.gateware.soc import AMPSoC
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from artiq.gateware import rtio, nist_qc1, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 10 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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ext_clkout = platform.request("user_sma_gpio_p")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=50, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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class _NIST_QCx(MiniSoC, AMPSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtio_crg": 13,
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"kernel_cpu": 14,
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"rtio_moninj": 15
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}
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csr_map.update(MiniSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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MiniSoC.__init__(self, platform,
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(l2_size=128*1024),
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with_timer=False, **kwargs)
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AMPSoC.__init__(self)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1)))
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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assert self.rtio.fine_ts_width <= 3
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.add_platform_command("""
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create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}]
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create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}]
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set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
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set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
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""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.add_platform_command("""
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NET "sys_clk" TNM_NET = "GRPrsys_clk";
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NET "{rio_clk}" TNM_NET = "GRPrio_clk";
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TIMESPEC "TSfix_cdc1" = FROM "GRPrsys_clk" TO "GRPrio_clk" TIG;
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TIMESPEC "TSfix_cdc2" = FROM "GRPrio_clk" TO "GRPrsys_clk" TIG;
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""", rio_clk=self.rtio_crg.cd_rtio.clk)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
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rtio_csrs)
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class NIST_QC1(_NIST_QCx):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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_NIST_QCx.__init__(self, platform, cpu_type, **kwargs)
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platform.add_extension(nist_qc1.fmc_adapter_io)
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_channels = []
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for i in range(2):
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phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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for i in range(15):
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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self.add_constant("DDS_AD9858")
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.add_rtio(rtio_channels)
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class NIST_QC2(_NIST_QCx):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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_NIST_QCx.__init__(self, platform, cpu_type, **kwargs)
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platform.add_extension(nist_qc2.fmc_adapter_io)
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rtio_channels = []
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for i in range(16):
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if i == 14:
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# TTL14 is for the clock generator
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continue
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if i % 4 == 3:
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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else:
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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phy = ttl_simple.ClockGen(platform.request("ttl", 14))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 11)
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self.add_constant("DDS_AD9914")
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self.add_constant("DDS_ONEHOT_SEL")
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phy = dds.AD9914(platform.request("dds"), 11)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.add_rtio(rtio_channels)
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default_subtarget = NIST_QC1
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