mirror of https://github.com/m-labs/artiq.git
57 lines
1.9 KiB
Python
57 lines
1.9 KiB
Python
import logging
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import unittest
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from migen import *
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from artiq.gateware.suservo import iir
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def main():
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w_kasli = iir.IIRWidths(state=25, coeff=18, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=3, profile=5, dly=8)
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w = iir.IIRWidths(state=17, coeff=16, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=2, profile=1, dly=8)
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def run(dut):
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for i, ch in enumerate(dut.adc):
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yield ch.eq(i)
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for i, ch in enumerate(dut.ctrl):
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yield ch.en_iir.eq(1)
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yield ch.en_out.eq(1)
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yield ch.profile.eq(i)
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for i in range(1 << w.channel):
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yield from dut.set_state(i, i << 8, coeff="x1")
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yield from dut.set_state(i, i << 8, coeff="x0")
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for j in range(1 << w.profile):
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yield from dut.set_state(i,
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(j << 1) | (i << 8), profile=j, coeff="y1")
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for k, l in enumerate("pow offset ftw0 ftw1".split()):
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yield from dut.set_coeff(i, profile=j, coeff=l,
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value=(i << 12) | (j << 8) | (k << 4))
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yield
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for i in range(1 << w.channel):
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for j in range(1 << w.profile):
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for k, l in enumerate("cfg a1 b0 b1".split()):
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yield from dut.set_coeff(i, profile=j, coeff=l,
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value=(i << 12) | (j << 8) | (k << 4))
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yield from dut.set_coeff(i, profile=j, coeff="cfg",
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value=(i << 0) | (j << 8)) # sel, dly
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yield
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for i in range(10):
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yield from dut.check_iter()
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yield
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dut = iir.IIR(w)
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run_simulation(dut, [run(dut)], vcd_name="iir.vcd")
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class IIRTest(unittest.TestCase):
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def test_run(self):
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main()
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if __name__ == "__main__":
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logging.basicConfig(level=logging.DEBUG)
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main()
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