mirror of https://github.com/m-labs/artiq.git
51 lines
1.6 KiB
Python
51 lines
1.6 KiB
Python
from migen.fhdl.std import *
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from mibuild.generic_platform import *
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from misoclib import gpio
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from targets.ppro import BaseSoC
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from artiqlib import rtio, ad9858
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_tester_io = [
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("user_led", 1, Pins("B:7"), IOStandard("LVTTL")),
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("ttl", 0, Pins("C:13"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:9"), IOStandard("LVTTL")),
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("ttl_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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class ARTIQMiniSoC(BaseSoC):
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csr_map = {
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"rtio": 10
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", 0),
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platform.request("user_led", 1)))
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self.comb += platform.request("ttl_tx_en").eq(1)
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rtio_pads = [platform.request("ttl", i) for i in range(4)]
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self.submodules.rtiophy = rtio.phy.SimplePHY(rtio_pads,
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{rtio_pads[1], rtio_pads[2], rtio_pads[3]})
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self.submodules.rtio = rtio.RTIO(self.rtiophy)
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self.submodules.dds = ad9858.AD9858(platform.request("dds"))
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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default_subtarget = ARTIQMiniSoC
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