mirror of https://github.com/m-labs/artiq
56 lines
1.4 KiB
Python
56 lines
1.4 KiB
Python
import unittest
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from migen import *
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from artiq.gateware.drtio.wrpll import thls
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a = 0
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def simple_test(x):
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global a
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a = a + (x*4 >> 1)
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return a
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class TestTHLS(unittest.TestCase):
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def test_thls(self):
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global a
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proc = thls.Processor()
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a = 0
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cp = thls.compile(proc, simple_test)
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print("Program:")
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cp.pretty_print()
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cp.dimension_processor()
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print("Encoded program:", cp.encode())
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proc_impl = proc.implement(cp.encode(), cp.data)
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def send_values(values):
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for value in values:
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yield proc_impl.input.eq(value)
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yield proc_impl.input_stb.eq(1)
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yield
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yield proc_impl.input.eq(0)
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yield proc_impl.input_stb.eq(0)
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yield
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while (yield proc_impl.busy):
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yield
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@passive
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def receive_values(callback):
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while True:
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while not (yield proc_impl.output_stb):
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yield
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callback((yield proc_impl.output))
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yield
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send_list = [42, 40, 10, 10]
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receive_list = []
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run_simulation(proc_impl, [send_values(send_list), receive_values(receive_list.append)])
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print("Execution:", send_list, "->", receive_list)
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a = 0
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expected_list = [simple_test(x) for x in send_list]
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self.assertEqual(receive_list, expected_list)
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