mirror of https://github.com/m-labs/artiq
281 lines
11 KiB
Python
Executable File
281 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import os
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import subprocess
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import struct
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores import spi2
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from misoc.cores.a7_gtp import *
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from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_argdict
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from misoc.integration.builder import Builder, builder_args, builder_argdict
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from artiq.gateware import rtio
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from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerGTP
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import add_identifier
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from artiq import __artiq_dir__ as artiq_dir
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class _SatelliteBase(BaseSoC):
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mem_map = {
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"drtioaux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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**kwargs)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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self.rtio_clk_freq = rtio_clk_freq
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platform = self.platform
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disable_cdrclkc_ibuf = Signal(reset=1)
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disable_cdrclkc_ibuf.attr.add("no_retiming")
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cdrclkc_clkout = platform.request("cdr_clk_clean")
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cdrclkc_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=disable_cdrclkc_ibuf,
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i_I=cdrclkc_clkout.p, i_IB=cdrclkc_clkout.n,
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o_O=cdrclkc_clkout_buf)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(cdrclkc_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[0],
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data_pads=[platform.request("rtm_amc_link", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += disable_cdrclkc_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw))
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self.submodules.drtioaux0 = coreaux
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self.csr_devices.append("drtioaux0")
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memory_address = self.mem_map["drtioaux"]
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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gtp = self.drtio_transceiver.gtps[0]
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if with_wrpll:
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self.comb += [
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platform.request("filtered_clk_sel").eq(0),
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platform.request("ddmtd_main_dcxo_oe").eq(1),
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platform.request("ddmtd_helper_dcxo_oe").eq(1)
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]
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self.submodules.wrpll_sampler = DDMTDSamplerGTP(
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self.drtio_transceiver,
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platform.request("cdr_clk_clean_fabric"))
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
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platform.add_false_path_constraints(self.wrpll.cd_helper.clk, gtp.rxoutclk)
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.cd_sys.clk, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.comb += self.drtiosat.cri.connect(self.local_io.cri)
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class Satellite(_SatelliteBase):
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def __init__(self, **kwargs):
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_SatelliteBase.__init__(self, **kwargs)
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platform = self.platform
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rtio_channels = []
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for bm in range(2):
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print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}"
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.format(bm, len(rtio_channels)))
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for i in range(4):
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phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i),
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invert=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}"
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.format(bm, len(rtio_channels)))
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basemod_att = platform.request("basemod{}_att".format(bm))
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for name in "rst_n clk le".split():
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signal = getattr(basemod_att, name)
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for i in range(len(signal)):
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phy = ttl_simple.Output(signal[i])
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(basemod_att.mosi[0])
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(3):
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self.comb += basemod_att.mosi[i+1].eq(basemod_att.miso[i])
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phy = ttl_simple.InOut(basemod_att.miso[3])
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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self.comb += platform.request("clk_src_ext_sel").eq(0)
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# HMC clock chip and DAC control
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self.comb += [
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platform.request("ad9154_rst_n", 0).eq(1),
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platform.request("ad9154_rst_n", 1).eq(1)
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]
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
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platform.request("hmc_spi"),
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platform.request("ad9154_spi", 0),
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platform.request("ad9154_spi", 1)))
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self.csr_devices.append("converter_spi")
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self.submodules.hmc7043_reset = gpio.GPIOOut(
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platform.request("hmc7043_reset"), reset_out=1)
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self.csr_devices.append("hmc7043_reset")
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self.submodules.hmc7043_gpo = gpio.GPIOIn(
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platform.request("hmc7043_gpo"))
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self.csr_devices.append("hmc7043_gpo")
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self.config["HAS_HMC830_7043"] = None
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self.config["HAS_AD9154"] = None
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self.config["AD9154_COUNT"] = 2
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self.config["CONVERTER_SPI_HMC830_CS"] = 0
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self.config["CONVERTER_SPI_HMC7043_CS"] = 1
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self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
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self.config["HMC830_REF"] = str(int(self.rtio_clk_freq/1e6))
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# HMC workarounds
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self.comb += platform.request("hmc830_pwr_en").eq(1)
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self.submodules.hmc7043_out_en = gpio.GPIOOut(
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platform.request("hmc7043_out_en"))
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self.csr_devices.append("hmc7043_out_en")
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# DDMTD
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sysref_pads = platform.request("rtm_fpga_sysref", 0)
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
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self.csr_devices.append("sysref_ddmtd")
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platform.add_false_path_constraints(
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self.sysref_ddmtd.cd_helper.clk, self.drtio_transceiver.gtps[0].txoutclk)
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platform.add_false_path_constraints(
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self.sysref_ddmtd.cd_helper.clk, self.crg.cd_sys.clk)
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class SatmanSoCBuilder(Builder):
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def __init__(self, *args, **kwargs):
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Builder.__init__(self, *args, **kwargs)
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firmware_dir = os.path.join(artiq_dir, "firmware")
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self.software_packages = []
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self.add_software_package("satman", os.path.join(firmware_dir, "satman"))
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def initialize_memory(self):
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satman = os.path.join(self.output_dir, "software", "satman",
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"satman.bin")
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with open(satman, "rb") as boot_file:
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boot_data = []
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unpack_endian = "<I"
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while True:
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w = boot_file.read(4)
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if not w:
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break
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boot_data.append(struct.unpack(unpack_endian, w)[0])
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self.soc.main_ram.mem.init = boot_data
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def main():
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parser = argparse.ArgumentParser(
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description="Sayma RTM gateware and firmware builder")
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builder_args(parser)
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soc_sayma_rtm_args(parser)
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parser.add_argument("--rtio-clk-freq",
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default=150, type=int, help="RTIO clock frequency in MHz")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm"))
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args = parser.parse_args()
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soc = Satellite(
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rtio_clk_freq=1e6*args.rtio_clk_freq,
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with_wrpll=args.with_wrpll,
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gateware_identifier_str=args.gateware_identifier_str,
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**soc_sayma_rtm_argdict(args))
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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try:
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builder.build()
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except subprocess.CalledProcessError as e:
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raise SystemExit("Command {} failed".format(" ".join(e.cmd)))
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if __name__ == "__main__":
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main()
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