mirror of https://github.com/m-labs/artiq
40 lines
1.3 KiB
Python
40 lines
1.3 KiB
Python
from collections import namedtuple
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from migen import *
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.dsp.sawg import Channel as _Channel
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_Phy = namedtuple("Phy", "rtlink probes overrides")
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_ChannelPHY = ClockDomainsRenamer("rio_phy")(_Channel)
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class Channel(_ChannelPHY):
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def __init__(self, *args, **kwargs):
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_ChannelPHY.__init__(self, *args, **kwargs)
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self.phys = []
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cfg = self.i[0]
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rl = rtlink.Interface(rtlink.OInterface(
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data_width=len(cfg.data), address_width=len(cfg.addr),
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enable_replace=False))
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self.comb += [
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cfg.stb.eq(rl.o.stb),
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rl.o.busy.eq(~cfg.ack),
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cfg.data.eq(rl.o.data),
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cfg.addr.eq(rl.o.address),
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]
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self.phys.append(_Phy(rl, [], []))
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for i in self.i[1:]:
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rl = rtlink.Interface(rtlink.OInterface(len(i.payload),
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delay=-i.latency))
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self.comb += [
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i.stb.eq(rl.o.stb),
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rl.o.busy.eq(~i.ack),
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i.payload.raw_bits().eq(rl.o.data),
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]
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# TODO probes, overrides
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self.phys.append(_Phy(rl, [], []))
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self.phys_named = dict(zip(self.i_names, self.phys))
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