mirror of https://github.com/m-labs/artiq
70 lines
2.1 KiB
Python
70 lines
2.1 KiB
Python
from operator import add
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from functools import reduce
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from migen import *
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class Delay(Module):
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def __init__(self, i, delay, o=None):
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if isinstance(i, (int, tuple)):
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z = [Signal(i) for j in range(delay + 1)]
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elif isinstance(i, list):
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z = [Record(i) for j in range(delay + 1)]
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elif isinstance(i, Record):
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z = [Record(i.layout) for j in range(delay + 1)]
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else:
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z = [Signal.like(i) for j in range(delay + 1)]
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self.i = z[0]
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self.o = z[-1]
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if not isinstance(i, (int, list, tuple)):
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self.comb += self.i.eq(i)
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if o is not None:
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self.comb += o.eq(self.o)
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self.latency = delay
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self.sync += [z[j + 1].eq(z[j]) for j in range(delay)]
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def eqh(a, b):
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return a[-len(b):].eq(b[-len(a):])
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class SatAddMixin:
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"""Signed saturating addition mixin"""
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def sat_add(self, a, width, limits=None, clipped=None):
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a = list(a)
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# assert all(value_bits_sign(ai)[1] for ai in a)
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max_width = max(value_bits_sign(ai)[0] for ai in a)
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carry = log2_int(len(a), need_pow2=False)
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full = Signal((max_width + carry, True))
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limited = Signal((width, True))
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carry = len(full) - width
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assert carry >= 0
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clip = Signal(2)
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sign = Signal()
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if clipped is not None:
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self.comb += clipped.eq(clip)
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self.comb += [
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full.eq(reduce(add, a)),
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sign.eq(full[-1]),
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limited.eq(full)
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]
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if limits is None:
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self.comb += [
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If(full[-1-carry:] != Replicate(sign, carry + 1),
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clip.eq(Cat(sign, ~sign)),
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limited.eq(Cat(Replicate(~sign, width - 1), sign)),
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)
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]
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else:
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self.comb += [
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If(full < limits[0],
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clip.eq(0b01),
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limited.eq(limits[0])
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),
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If(full > limits[1],
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clip.eq(0b10),
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limited.eq(limits[1]),
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)
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]
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return limited
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