mirror of https://github.com/m-labs/artiq
341 lines
9.1 KiB
Python
341 lines
9.1 KiB
Python
from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer, BlindTransfer
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from misoc.interconnect.csr import *
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class I2CClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.clk2x = Signal()
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cnt = Signal.like(self.load)
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self.comb += [
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self.clk2x.eq(cnt == 0),
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]
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self.sync += [
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If(self.clk2x,
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cnt.eq(self.load),
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).Else(
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cnt.eq(cnt - 1),
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)
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]
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class I2CMasterMachine(Module):
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def __init__(self, clock_width):
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self.scl = Signal(reset=1)
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self.sda_o = Signal(reset=1)
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self.sda_i = Signal()
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self.submodules.cg = CEInserter()(I2CClockGen(clock_width))
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self.start = Signal()
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self.stop = Signal()
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self.write = Signal()
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self.ack = Signal()
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self.data = Signal(8)
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self.ready = Signal()
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###
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bits = Signal(4)
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data = Signal(8)
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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self.ready.eq(1),
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If(self.start,
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NextState("START0"),
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).Elif(self.stop,
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NextState("STOP0"),
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).Elif(self.write,
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NextValue(bits, 8),
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NextValue(data, self.data),
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NextState("WRITE0")
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)
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)
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fsm.act("START0",
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NextValue(self.scl, 1),
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NextState("START1")
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)
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fsm.act("START1",
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NextValue(self.sda_o, 0),
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NextState("IDLE")
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)
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fsm.act("STOP0",
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NextValue(self.scl, 0),
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NextState("STOP1")
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)
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fsm.act("STOP1",
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NextValue(self.sda_o, 0),
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NextState("STOP2")
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)
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fsm.act("STOP2",
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NextValue(self.scl, 1),
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NextState("STOP3")
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)
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fsm.act("STOP3",
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NextValue(self.sda_o, 1),
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NextState("IDLE")
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)
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fsm.act("WRITE0",
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NextValue(self.scl, 0),
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NextState("WRITE1")
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)
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fsm.act("WRITE1",
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If(bits == 0,
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, data[7]),
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NextState("WRITE2"),
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)
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)
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fsm.act("WRITE2",
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NextValue(self.scl, 1),
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NextValue(data[1:], data[:-1]),
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NextValue(bits, bits - 1),
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NextState("WRITE0"),
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)
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fsm.act("READACK0",
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NextValue(self.scl, 1),
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NextState("READACK1"),
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)
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fsm.act("READACK1",
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NextValue(self.ack, ~self.sda_i),
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NextState("IDLE")
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)
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run = Signal()
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idle = Signal()
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self.comb += [
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run.eq((self.start | self.stop | self.write) & self.ready),
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idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~idle),
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fsm.ce.eq(run | self.cg.clk2x),
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]
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class ADPLLProgrammer(Module):
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def __init__(self):
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self.i2c_divider = Signal(16)
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self.i2c_address = Signal(7)
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self.adpll = Signal(24)
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self.stb = Signal()
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self.busy = Signal()
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self.nack = Signal()
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self.scl = Signal()
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self.sda_i = Signal()
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self.sda_o = Signal()
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self.scl.attr.add("no_retiming")
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self.sda_o.attr.add("no_retiming")
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# # #
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master = I2CMasterMachine(16)
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self.submodules += master
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self.comb += [
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master.cg.load.eq(self.i2c_divider),
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self.scl.eq(master.scl),
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master.sda_i.eq(self.sda_i),
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self.sda_o.eq(master.sda_o)
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]
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fsm = FSM()
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self.submodules += fsm
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adpll = Signal.like(self.adpll)
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fsm.act("IDLE",
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If(self.stb,
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NextValue(adpll, self.adpll),
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NextState("START")
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)
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)
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fsm.act("START",
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master.start.eq(1),
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If(master.ready, NextState("DEVADDRESS"))
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)
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fsm.act("DEVADDRESS",
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master.data.eq(self.i2c_address << 1),
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master.write.eq(1),
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If(master.ready, NextState("REGADRESS"))
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)
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fsm.act("REGADRESS",
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master.data.eq(231),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA0")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA0",
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master.data.eq(adpll[0:8]),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA1")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA1",
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master.data.eq(adpll[8:16]),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA2")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA2",
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master.data.eq(adpll[16:24]),
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master.write.eq(1),
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If(master.ready,
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If(~master.ack, self.nack.eq(1)),
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NextState("STOP")
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)
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)
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fsm.act("STOP",
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master.stop.eq(1),
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If(master.ready,
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If(~master.ack, self.nack.eq(1)),
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NextState("IDLE")
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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def simulate_programmer():
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from migen.sim.core import run_simulation
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dut = ADPLLProgrammer()
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def generator():
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yield dut.i2c_divider.eq(4)
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yield dut.i2c_address.eq(0x55)
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yield
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yield dut.adpll.eq(0x123456)
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yield dut.stb.eq(1)
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yield
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yield dut.stb.eq(0)
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yield
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while (yield dut.busy):
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yield
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for _ in range(20):
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yield
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run_simulation(dut, generator(), vcd_name="tb.vcd")
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class Si549(Module, AutoCSR):
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def __init__(self, pads):
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self.gpio_enable = CSRStorage(reset=1)
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self.gpio_in = CSRStatus(2)
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self.gpio_out = CSRStorage(2)
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self.gpio_oe = CSRStorage(2)
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self.i2c_divider = CSRStorage(16, reset=75)
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self.i2c_address = CSRStorage(7)
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self.errors = CSR(2)
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# in helper clock domain
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self.adpll = Signal(24)
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self.adpll_stb = Signal()
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# # #
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programmer = ClockDomainsRenamer("helper")(ADPLLProgrammer())
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self.submodules += programmer
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self.i2c_divider.storage.attr.add("no_retiming")
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self.i2c_address.storage.attr.add("no_retiming")
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self.specials += [
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MultiReg(self.i2c_divider.storage, programmer.i2c_divider, "helper"),
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MultiReg(self.i2c_address.storage, programmer.i2c_address, "helper")
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]
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self.comb += [
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programmer.adpll.eq(self.adpll),
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programmer.stb.eq(self.adpll_stb)
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]
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self.gpio_enable.storage.attr.add("no_retiming")
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self.gpio_out.storage.attr.add("no_retiming")
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self.gpio_oe.storage.attr.add("no_retiming")
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# SCL GPIO and mux
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ts_scl = TSTriple(1)
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self.specials += ts_scl.get_tristate(pads.scl)
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status = Signal()
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self.comb += self.gpio_in.status[0].eq(status)
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self.specials += MultiReg(ts_scl.i, status)
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self.comb += [
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If(self.gpio_enable.storage,
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ts_scl.o.eq(self.gpio_out.storage[0]),
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ts_scl.oe.eq(self.gpio_oe.storage[0])
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).Else(
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ts_scl.o.eq(0),
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ts_scl.oe.eq(~programmer.scl)
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)
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]
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# SDA GPIO and mux
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ts_sda = TSTriple(1)
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self.specials += ts_sda.get_tristate(pads.sda)
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status = Signal()
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self.comb += self.gpio_in.status[1].eq(status)
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self.specials += MultiReg(ts_sda.i, status)
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self.comb += [
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If(self.gpio_enable.storage,
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ts_sda.o.eq(self.gpio_out.storage[1]),
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ts_sda.oe.eq(self.gpio_oe.storage[1])
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).Else(
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ts_sda.o.eq(0),
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ts_sda.oe.eq(~programmer.sda_o)
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)
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]
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self.specials += MultiReg(ts_sda.i, programmer.sda_i, "helper")
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# Error reporting
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collision_cdc = BlindTransfer("helper", "sys")
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self.submodules += collision_cdc
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self.comb += collision_cdc.i.eq(programmer.stb & programmer.busy)
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nack_cdc = PulseSynchronizer("helper", "sys")
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self.submodules += nack_cdc
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self.comb += nack_cdc.i.eq(programmer.nack)
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for n, trig in enumerate([collision_cdc.o, nack_cdc.o]):
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self.sync += [
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If(self.errors.re & self.errors.r[n], self.errors.w[n].eq(0)),
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If(trig, self.errors.w[n].eq(1))
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]
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if __name__ == "__main__":
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simulate_programmer()
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