artiq/artiq/gateware/drtio/transceiver
Alex Wong Tat Hang a3ae82502c
gtx_7series: fix IBUFGS_GTE2 buffer parameters
Co-authored-by: topquark12 <aw@m-labs.hk>
2022-08-01 10:21:28 +08:00
..
__init__.py drtio: GTX WIP 2016-10-14 00:36:13 +08:00
clock_aligner.py add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
gth_ultrascale.py sayma: fix/cleanup DRTIO-DAC sync interaction 2020-04-06 22:34:05 +08:00
gth_ultrascale_init.py drtio/gth: cleanup import 2018-03-06 10:56:07 +01:00
gtp_7series.py sayma: fix/cleanup DRTIO-DAC sync interaction 2020-04-06 22:34:05 +08:00
gtp_7series_init.py drtio/transceiver/gtp: implement tx multi lane phase alignment sequence 2018-02-27 12:32:25 +01:00
gtx_7series.py gtx_7series: fix IBUFGS_GTE2 buffer parameters 2022-08-01 10:21:28 +08:00
gtx_7series_init.py kc705: cleanup 2021-01-22 11:11:13 +08:00