mirror of https://github.com/m-labs/artiq
90 lines
2.8 KiB
Python
90 lines
2.8 KiB
Python
from artiq.experiment import *
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class SinesUrukulSayma(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("urukul0_cpld")
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# Urukul clock output syntonized to the RTIO clock.
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# Can be used as HMC830 reference on Sayma RTM.
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# When using this reference, Sayma must be recalibrated every time Urukul
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# is rebooted, as Urukul is not synchronized to the Kasli.
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self.urukul_hmc_ref = self.get_device("urukul0_ch3")
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# Urukul measurement channels - compare with SAWG outputs.
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# When testing sync, do not reboot Urukul, as it is not
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# synchronized to the Kasli.
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self.urukul_meas = [self.get_device("urukul0_ch" + str(i)) for i in range(3)]
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# The same waveform is output on all first 4 SAWG channels (first DAC).
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(4)]
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self.basemod = self.get_device("basemod_att0")
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self.rfsws = [self.get_device("sawg_sw"+str(i)) for i in range(4)]
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# DRTIO destinations:
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# 0: local
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# 1: Sayma AMC
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# 2: Sayma RTM
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@kernel
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def drtio_is_up(self):
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for i in range(3):
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if not self.core.get_rtio_destination_status(i):
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return False
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return True
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@kernel
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def run(self):
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f = 9*MHz
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dds_ftw = self.urukul_meas[0].frequency_to_ftw(f)
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sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
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if dds_ftw != sawg_ftw:
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print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
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return
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self.core.reset()
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self.urukul0_cpld.init()
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delay(1*ms)
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self.urukul_hmc_ref.init()
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self.urukul_hmc_ref.set_mu(0x40000000, asf=self.urukul_hmc_ref.amplitude_to_asf(0.6))
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self.urukul_hmc_ref.set_att(6.)
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self.urukul_hmc_ref.sw.on()
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for urukul_ch in self.urukul_meas:
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delay(1*ms)
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urukul_ch.init()
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urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
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urukul_ch.set_att(6.)
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urukul_ch.sw.on()
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while True:
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print("waiting for DRTIO ready...")
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while not self.drtio_is_up():
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pass
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print("OK")
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self.core.reset()
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delay(10*ms)
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self.basemod.reset()
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delay(10*ms)
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self.basemod.set(3.0, 3.0, 3.0, 3.0)
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delay(10*ms)
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for rfsw in self.rfsws:
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delay(1*ms)
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rfsw.on()
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.reset()
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.amplitude1.set(.4)
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sawg.frequency0.set_mu(sawg_ftw)
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sawg.phase0.set_mu(sawg_ftw*now_mu() >> 17)
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while self.drtio_is_up():
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pass
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