mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-21 09:26:29 +08:00
141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
#include <generated/csr.h>
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#include <stdio.h>
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#include "exceptions.h"
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#include "rtio.h"
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#include "dds.h"
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#define DURATION_WRITE 5
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#define DURATION_INIT (7*DURATION_WRITE) /* not counting FUD */
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#define DURATION_PROGRAM (8*DURATION_WRITE) /* not counting FUD */
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#define DDS_WRITE(addr, data) do { \
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rtio_o_address_write(addr); \
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rtio_o_data_write(data); \
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rtio_o_timestamp_write(now); \
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rtio_write_and_process_status(now, RTIO_DDS_CHANNEL); \
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now += DURATION_WRITE; \
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} while(0)
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void dds_init_all(void)
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{
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int i;
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long long int now;
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now = rtio_get_counter() + 10000;
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for(i=0;i<DDS_CHANNEL_COUNT;i++) {
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dds_init(now, i);
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now += DURATION_INIT + DURATION_WRITE; /* + FUD time */
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}
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while(rtio_get_counter() < now);
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}
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void dds_init(long long int timestamp, int channel)
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{
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long long int now;
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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now = timestamp - DURATION_INIT;
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(DDS_GPIO, channel | (1 << 7));
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(0x00, 0x78);
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DDS_WRITE(0x01, 0x00);
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DDS_WRITE(0x02, 0x00);
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DDS_WRITE(0x03, 0x00);
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DDS_WRITE(DDS_FUD, 0);
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}
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static void dds_set_one(long long int now, long long int ref_time, int channel,
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unsigned int ftw, unsigned int pow, int phase_mode)
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{
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DDS_WRITE(DDS_GPIO, channel);
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if(phase_mode == PHASE_MODE_CONTINUOUS)
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/* Do not clear phase accumulator on FUD */
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DDS_WRITE(0x02, 0x00);
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else
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/* Clear phase accumulator on FUD */
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DDS_WRITE(0x02, 0x40);
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DDS_WRITE(DDS_FTW0, ftw & 0xff);
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DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
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DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
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DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
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/* We assume that the RTIO clock is DDS SYNCLK */
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if(phase_mode == PHASE_MODE_TRACKING)
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pow += (ref_time >> RTIO_FINE_TS_WIDTH)*ftw >> 18;
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if(phase_mode != PHASE_MODE_CONTINUOUS) {
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long long int fud_time;
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fud_time = now + 2*DURATION_WRITE;
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pow -= ((ref_time - fud_time) >> RTIO_FINE_TS_WIDTH)*ftw >> 18;
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}
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DDS_WRITE(DDS_POW0, pow & 0xff);
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DDS_WRITE(DDS_POW1, (pow >> 8) & 0x3f);
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DDS_WRITE(DDS_FUD, 0);
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}
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struct dds_set_params {
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int channel;
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unsigned int ftw;
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unsigned int pow;
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int phase_mode;
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};
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static int batch_mode;
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static int batch_count;
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static long long int batch_ref_time;
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static struct dds_set_params batch[DDS_MAX_BATCH];
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void dds_batch_enter(long long int timestamp)
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{
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if(batch_mode)
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exception_raise(EID_DDS_BATCH_ERROR);
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batch_mode = 1;
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batch_count = 0;
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batch_ref_time = timestamp;
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}
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void dds_batch_exit(void)
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{
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long long int now;
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int i;
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if(!batch_mode)
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exception_raise(EID_DDS_BATCH_ERROR);
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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/* + FUD time */
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now = batch_ref_time - batch_count*(DURATION_PROGRAM + DURATION_WRITE);
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for(i=0;i<batch_count;i++) {
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dds_set_one(now, batch_ref_time,
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batch[i].channel, batch[i].ftw, batch[i].pow, batch[i].phase_mode);
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now += DURATION_PROGRAM + DURATION_WRITE;
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}
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batch_mode = 0;
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}
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void dds_set(long long int timestamp, int channel,
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unsigned int ftw, unsigned int pow, int phase_mode)
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{
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if(batch_mode) {
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if(batch_count >= DDS_MAX_BATCH)
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exception_raise(EID_DDS_BATCH_ERROR);
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/* timestamp parameter ignored (determined by batch) */
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batch[batch_count].channel = channel;
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batch[batch_count].ftw = ftw;
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batch[batch_count].pow = pow;
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batch[batch_count].phase_mode = phase_mode;
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batch_count++;
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} else {
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rtio_chan_sel_write(RTIO_DDS_CHANNEL);
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dds_set_one(timestamp - DURATION_PROGRAM, timestamp, channel, ftw, pow, phase_mode);
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}
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}
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