mirror of https://github.com/m-labs/artiq.git
62 lines
1.9 KiB
Python
62 lines
1.9 KiB
Python
from migen import *
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from migen.genlib.cdc import *
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__all__ = ["GrayCodeTransfer", "BlindTransfer"]
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# note: transfer is in rtio/sys domains and not affected by the reset CSRs
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class GrayCodeTransfer(Module):
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def __init__(self, width):
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self.i = Signal(width) # in rtio domain
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self.o = Signal(width) # in sys domain
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# # #
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# convert to Gray code
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value_gray_rtio = Signal(width)
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self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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value_gray_rtio.attr.add("no_retiming")
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self.specials += MultiReg(value_gray_rtio, value_gray_sys)
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# convert back to binary
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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for i in reversed(range(width-1)):
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self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
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self.sync += self.o.eq(value_sys)
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class BlindTransfer(Module):
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def __init__(self, idomain="rio", odomain="rsys", data_width=0):
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self.i = Signal()
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self.o = Signal()
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if data_width:
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self.data_i = Signal(data_width)
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self.data_o = Signal(data_width)
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# # #
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ps = PulseSynchronizer(idomain, odomain)
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ps_ack = PulseSynchronizer(odomain, idomain)
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self.submodules += ps, ps_ack
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blind = Signal()
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isync = getattr(self.sync, idomain)
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isync += [
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If(self.i, blind.eq(1)),
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If(ps_ack.o, blind.eq(0))
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]
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self.comb += [
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ps.i.eq(self.i & ~blind),
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ps_ack.i.eq(ps.o),
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self.o.eq(ps.o)
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]
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if data_width:
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bxfer_data = Signal(data_width)
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isync += If(ps.i, bxfer_data.eq(self.data_i))
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bxfer_data.attr.add("no_retiming")
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self.specials += MultiReg(bxfer_data, self.data_o,
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odomain=odomain)
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