Robert Jördens 67715f0d2e pipistrello: only put serdes on the lower ttls ... this setup is getting a bit power hungry. pmt0, 1 (rtio channels 0, 1): 4x in and out ttl0, 1 (rtio channels 2, 3): 4x out ttl2 (rtio channel 4): 8x out		2015-07-28 12:54:31 -06:00
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artiq_kc705.py	kc705: generate 10MHz clock on GPIO SMA	2015-07-28 18:56:47 +08:00
artiq_pipistrello.py	pipistrello: only put serdes on the lower ttls	2015-07-28 12:54:31 -06:00