mirror of https://github.com/m-labs/artiq.git
289 lines
9.1 KiB
Rust
289 lines
9.1 KiB
Rust
mod i2c {
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use board_misoc::{csr, clock};
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#[derive(Debug, Clone, Copy)]
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pub enum Dcxo {
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Main,
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Helper
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}
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fn half_period() { clock::spin_us(100) }
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const SDA_MASK: u8 = 2;
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const SCL_MASK: u8 = 1;
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fn sda_i(dcxo: Dcxo) -> bool {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_in_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_in_read() },
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};
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reg & SDA_MASK != 0
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}
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fn sda_oe(dcxo: Dcxo, oe: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_read() },
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};
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let reg = if oe { reg | SDA_MASK } else { reg & !SDA_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_write(reg) }
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}
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}
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fn sda_o(dcxo: Dcxo, o: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_read() },
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};
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let reg = if o { reg | SDA_MASK } else { reg & !SDA_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_write(reg) }
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}
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}
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fn scl_oe(dcxo: Dcxo, oe: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_read() },
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};
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let reg = if oe { reg | SCL_MASK } else { reg & !SCL_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_write(reg) }
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}
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}
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fn scl_o(dcxo: Dcxo, o: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_read() },
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};
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let reg = if o { reg | SCL_MASK } else { reg & !SCL_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_write(reg) }
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}
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}
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pub fn init(dcxo: Dcxo) -> Result<(), &'static str> {
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// Set SCL as output, and high level
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scl_o(dcxo, true);
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scl_oe(dcxo, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(dcxo, false);
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// Release SDA
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sda_oe(dcxo, false);
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// Check the I2C bus is ready
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half_period();
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half_period();
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if !sda_i(dcxo) {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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scl_o(dcxo, false);
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half_period();
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scl_o(dcxo, true);
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half_period();
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}
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}
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if !sda_i(dcxo) {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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Ok(())
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}
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pub fn start(dcxo: Dcxo) {
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// Set SCL high then SDA low
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scl_o(dcxo, true);
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half_period();
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sda_oe(dcxo, true);
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half_period();
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}
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pub fn restart(dcxo: Dcxo) {
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// Set SCL low then SDA high */
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scl_o(dcxo, false);
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half_period();
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sda_oe(dcxo, false);
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half_period();
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// Do a regular start
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start(dcxo);
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}
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pub fn stop(dcxo: Dcxo) {
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(dcxo, false);
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half_period();
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// Set SCL high then SDA high
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sda_oe(dcxo, true);
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scl_o(dcxo, true);
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half_period();
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sda_oe(dcxo, false);
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half_period();
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}
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pub fn write(dcxo: Dcxo, data: u8) -> bool {
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(dcxo, false);
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sda_oe(dcxo, data & (1 << bit) == 0);
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half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(dcxo, true);
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half_period();
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(dcxo, false);
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half_period();
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sda_oe(dcxo, false);
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// Set SCL high and check for ack
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scl_o(dcxo, true);
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half_period();
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(dcxo)
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}
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pub fn read(dcxo: Dcxo, ack: bool) -> u8 {
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(dcxo, false);
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half_period(); // make sure SCL has settled low
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sda_oe(dcxo, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(dcxo, false);
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half_period();
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// Set SCL high and shift data
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scl_o(dcxo, true);
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half_period();
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if sda_i(dcxo) { data |= 1 << bit }
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(dcxo, false);
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if ack { sda_oe(dcxo, true) }
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half_period();
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// then set SCL high
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scl_o(dcxo, true);
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half_period();
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data
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}
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}
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mod si549 {
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use board_misoc::clock;
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use super::i2c;
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const ADDRESS: u8 = 0x55;
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pub fn write(dcxo: i2c::Dcxo, reg: u8, val: u8) -> Result<(), &'static str> {
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i2c::start(dcxo);
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if !i2c::write(dcxo, ADDRESS << 1) {
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return Err("Si549 failed to ack write address")
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}
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if !i2c::write(dcxo, reg) {
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return Err("Si549 failed to ack register")
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}
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if !i2c::write(dcxo, val) {
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return Err("Si549 failed to ack value")
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}
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i2c::stop(dcxo);
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Ok(())
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}
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pub fn write_no_ack_value(dcxo: i2c::Dcxo, reg: u8, val: u8) -> Result<(), &'static str> {
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i2c::start(dcxo);
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if !i2c::write(dcxo, ADDRESS << 1) {
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return Err("Si549 failed to ack write address")
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}
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if !i2c::write(dcxo, reg) {
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return Err("Si549 failed to ack register")
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}
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i2c::write(dcxo, val);
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i2c::stop(dcxo);
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Ok(())
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}
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pub fn read(dcxo: i2c::Dcxo, reg: u8) -> Result<u8, &'static str> {
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i2c::start(dcxo);
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if !i2c::write(dcxo, ADDRESS << 1) {
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return Err("Si549 failed to ack write address")
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}
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if !i2c::write(dcxo, reg) {
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return Err("Si549 failed to ack register")
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}
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i2c::restart(dcxo);
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if !i2c::write(dcxo, (ADDRESS << 1) | 1) {
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return Err("Si549 failed to ack read address")
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}
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let val = i2c::read(dcxo, false);
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i2c::stop(dcxo);
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Ok(val)
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}
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pub fn program(dcxo: i2c::Dcxo, hsdiv: u16, lsdiv: u8, fbdiv: u64) -> Result<(), &'static str> {
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i2c::init(dcxo)?;
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write(dcxo, 255, 0x00)?; // PAGE
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write_no_ack_value(dcxo, 7, 0x80)?; // RESET
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clock::spin_us(50_000); // required? not specified in datasheet.
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write(dcxo, 255, 0x00)?; // PAGE
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write(dcxo, 69, 0x00)?; // Disable FCAL override.
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// Note: Value 0x00 from Table 5.6 is inconsistent with Table 5.7,
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// which shows bit 0 as reserved and =1.
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write(dcxo, 17, 0x00)?; // Synchronously disable output
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// The Si549 has no ID register, so we check that it responds correctly
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// by writing values to a RAM-like register and reading them back.
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for test_value in 0..255 {
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write(dcxo, 23, test_value)?;
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let readback = read(dcxo, 23)?;
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if readback != test_value {
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return Err("Si549 detection failed");
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}
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}
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write(dcxo, 23, hsdiv as u8)?;
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write(dcxo, 24, (hsdiv >> 8) as u8 | (lsdiv << 4))?;
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write(dcxo, 26, fbdiv as u8)?;
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write(dcxo, 27, (fbdiv >> 8) as u8)?;
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write(dcxo, 28, (fbdiv >> 16) as u8)?;
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write(dcxo, 29, (fbdiv >> 24) as u8)?;
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write(dcxo, 30, (fbdiv >> 32) as u8)?;
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write(dcxo, 31, (fbdiv >> 40) as u8)?;
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write(dcxo, 7, 0x08)?; // Start FCAL
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write(dcxo, 17, 0x01)?; // Synchronously enable output
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Ok(())
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}
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}
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pub fn init() {
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info!("initializing...");
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#[cfg(rtio_frequency = "125.0")]
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let (m_hsdiv, m_lsdiv, m_fbdiv) = (0x017, 2, 0x04b5badb98a);
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#[cfg(rtio_frequency = "125.0")]
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let (h_hsdiv, h_lsdiv, h_fbdiv) = (0x017, 2, 0x04b5c447213);
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si549::program(i2c::Dcxo::Main, m_hsdiv, m_lsdiv, m_fbdiv)
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.expect("cannot initialize main Si549");
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si549::program(i2c::Dcxo::Helper, h_hsdiv, h_lsdiv, h_fbdiv)
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.expect("cannot initialize helper Si549");
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}
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pub fn select_recovered_clock(rc: bool) {
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info!("select_recovered_clock: {}", rc);
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}
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