mirror of https://github.com/m-labs/artiq.git
32 lines
631 B
Python
32 lines
631 B
Python
import numpy as np
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.spline import Spline
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from .tools import xfer
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def _test_gen_spline(dut, o):
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yield dut.o.ack.eq(1)
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yield from xfer(dut, i=dict(a0=0, a1=1, a2=2))
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for i in range(20):
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yield
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o.append((yield dut.o.a0))
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def _test_spline():
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dut = Spline(order=3, width=16, step=1)
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if False:
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print(convert(dut))
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else:
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o = []
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run_simulation(dut, _test_gen_spline(dut, o), vcd_name="spline.vcd")
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o = np.array(o)
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print(o)
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if __name__ == "__main__":
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_test_spline()
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