mirror of https://github.com/m-labs/artiq.git
447 lines
15 KiB
Python
447 lines
15 KiB
Python
from math import log, sqrt
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import logging
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import struct
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import serial
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from artiq.wavesynth.coefficients import discrete_compensate
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from artiq.language.core import portable
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logger = logging.getLogger(__name__)
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class Segment:
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"""Serialize the lines for a single Segment.
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Attributes:
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max_time (int): Maximum duration of a line.
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max_val (int): Maximum absolute value (scale) of the DAC output.
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max_out (float): Output voltage at :attr:`max_val`. In Volt.
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out_scale (float): Steps per Volt.
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cordic_gain (float): CORDIC amplitude gain.
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addr (int): Address assigned to this segment.
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data (bytes): Serialized segment data.
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"""
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max_time = 1 << 16 # uint16 timer
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max_val = 1 << 15 # int16 DAC
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max_out = 10. # Volt
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out_scale = max_val/max_out
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cordic_gain = 1.
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for i in range(16):
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cordic_gain *= sqrt(1 + 2**(-2*i))
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def __init__(self):
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self.data = b""
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self.addr = None
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def line(self, typ, duration, data, trigger=False, silence=False,
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aux=False, shift=0, jump=False, clear=False, wait=False):
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"""Append a line to this segment.
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Args:
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typ (int): Output module to target with this line.
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duration (int): Duration of the line in units of
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``clock_period*2**shift``.
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data (bytes): Opaque data for the output module.
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trigger (bool): Wait for trigger assertion before executing
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this line.
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silence (bool): Disable DAC clocks for the duration of this line.
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aux (bool): Assert the AUX (F5 TTL) output during this line.
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The corresponding global AUX routing setting determines which
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channels control AUX.
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shift (int): Duration and spline evolution exponent.
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jump (bool): Return to the frame address table after this line.
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clear (bool): Clear the DDS phase accumulator when starting to
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exectute this line.
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wait (bool): Wait for trigger assertion before executing the next
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line.
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"""
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assert len(data) % 2 == 0, data
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assert len(data)//2 <= 14
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# assert dt*(1 << shift) > 1 + len(data)//2
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header = (
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1 + len(data)//2 | (typ << 4) | (trigger << 6) | (silence << 7) |
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(aux << 8) | (shift << 9) | (jump << 13) | (clear << 14) |
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(wait << 15)
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)
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self.data += struct.pack("<HH", header, duration) + data
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@staticmethod
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def pack(widths, values):
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"""Pack spline data.
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Args:
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widths (list[int]): Widths of values in multiples of 16 bits.
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values (list[int]): Values to pack.
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Returns:
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data (bytes): Packed data.
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"""
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fmt = "<"
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ud = []
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for width, value in zip(widths, values):
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value = int(round(value * (1 << 16*width)))
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if width == 2:
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ud.append(value & 0xffff)
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fmt += "H"
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value >>= 16
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width -= 1
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ud.append(value)
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fmt += "hi"[width]
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try:
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return struct.pack(fmt, *ud)
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except struct.error as e:
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logger.error("can not pack %s as %s (%s as %s): %s",
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values, widths, ud, fmt, e)
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raise e
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def bias(self, amplitude=[], **kwargs):
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"""Append a bias line to this segment.
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Args:
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amplitude (list[float]): Amplitude coefficients in in Volts and
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increasing powers of ``1/(2**shift*clock_period)``.
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Discrete time compensation will be applied.
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**kwargs: Passed to :meth:`line`.
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"""
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coef = [self.out_scale*a for a in amplitude]
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discrete_compensate(coef)
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data = self.pack([0, 1, 2, 2], coef)
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self.line(typ=0, data=data, **kwargs)
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def dds(self, amplitude=[], phase=[], **kwargs):
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"""Append a DDS line to this segment.
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Args:
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amplitude (list[float]): Amplitude coefficients in in Volts and
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increasing powers of ``1/(2**shift*clock_period)``.
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Discrete time compensation and CORDIC gain compensation
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will be applied by this method.
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phase (list[float]): Phase/frequency/chirp coefficients.
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``phase[0]`` in ``turns``,
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``phase[1]`` in ``turns/clock_period``,
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``phase[2]`` in ``turns/(clock_period**2*2**shift)``.
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**kwargs: Passed to :meth:`line`.
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"""
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scale = self.out_scale/self.cordic_gain
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coef = [scale*a for a in amplitude]
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discrete_compensate(coef)
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if phase:
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assert len(amplitude) == 4
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coef += [p*self.max_val*2 for p in phase]
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data = self.pack([0, 1, 2, 2, 0, 1, 1], coef)
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self.line(typ=1, data=data, **kwargs)
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class Channel:
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"""PDQ Channel.
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Attributes:
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num_frames (int): Number of frames supported.
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max_data (int): Number of 16 bit data words per channel.
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segments (list[Segment]): Segments added to this channel.
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"""
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def __init__(self, max_data, num_frames):
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self.max_data = max_data
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self.num_frames = num_frames
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self.segments = []
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def clear(self):
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"""Remove all segments."""
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self.segments.clear()
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def new_segment(self):
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"""Create and attach a new :class:`Segment` to this channel.
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Returns:
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:class:`Segment`
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"""
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segment = Segment()
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self.segments.append(segment)
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return segment
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def place(self):
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"""Place segments contiguously.
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Assign segment start addresses and determine length of data.
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Returns:
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addr (int): Amount of memory in use on this channel.
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"""
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addr = self.num_frames
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for segment in self.segments:
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segment.addr = addr
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addr += len(segment.data)//2
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assert addr <= self.max_data, addr
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return addr
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def table(self, entry=None):
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"""Generate the frame address table.
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Unused frame indices are assigned the zero address in the frame address
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table.
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This will cause the memory parser to remain in the frame address table
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until another frame is selected.
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The frame entry segments can be any segments in the channel.
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Args:
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entry (list[Segment]): List of initial segments for each frame.
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If not specified, the first :attr:`num_frames` segments are
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used as frame entry points.
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Returns:
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table (bytes): Frame address table.
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"""
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table = [0] * self.num_frames
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if entry is None:
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entry = self.segments
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for i, frame in enumerate(entry):
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if frame is not None:
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table[i] = frame.addr
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return struct.pack("<" + "H"*self.num_frames, *table)
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def serialize(self, entry=None):
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"""Serialize the memory for this channel.
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Places the segments contiguously in memory after the frame table.
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Allocates and assigns segment and frame table addresses.
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Serializes segment data and prepends frame address table.
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Args:
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entry (list[Segment]): See :meth:`table`.
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Returns:
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data (bytes): Channel memory data.
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"""
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self.place()
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data = b"".join([segment.data for segment in self.segments])
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return self.table(entry) + data
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@portable
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def PDQ_CMD(board, is_mem, adr, we):
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"""Pack PDQ command fields into command byte.
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:param board: Board address, 0 to 15, with ``15 = 0xf`` denoting broadcast
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to all boards connected.
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:param is_mem: If ``1``, ``adr`` denote the address of the memory to access
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(0 to 2). Otherwise ``adr`` denotes the register to access.
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:param adr: Address of the register or memory to access.
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(``PDQ_ADR_CONFIG``, ``PDQ_ADR_FRAME``, ``PDQ_ADR_CRC``).
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:param we: If ``1`` then write, otherwise read.
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"""
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return (adr << 0) | (is_mem << 2) | (board << 3) | (we << 7)
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PDQ_ADR_CONFIG = 0
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PDQ_ADR_CRC = 1
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PDQ_ADR_FRAME = 2
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class PDQBase:
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"""
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PDQ stack.
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Attributes:
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checksum (int): Running checksum of data written.
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num_channels (int): Number of channels in this stack.
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num_boards (int): Number of boards in this stack.
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num_dacs (int): Number of DAC outputs per board.
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num_frames (int): Number of frames supported.
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channels (list[Channel]): List of :class:`Channel` in this stack.
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"""
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freq = 50e6
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_mem_sizes = [None, (20,), (10, 10), (8, 6, 6)] # 10kx16 units
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def __init__(self, num_boards=3, num_dacs=3, num_frames=32):
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"""Initialize PDQ stack.
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Args:
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num_boards (int): Number of boards in this stack.
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num_dacs (int): Number of DAC outputs per board.
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num_frames (int): Number of frames supported.
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"""
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self.checksum = 0
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self.num_boards = num_boards
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self.num_dacs = num_dacs
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self.num_frames = num_frames
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self.num_channels = self.num_dacs * self.num_boards
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m = self._mem_sizes[num_dacs]
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self.channels = [Channel(m[j] << 11, num_frames)
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for i in range(num_boards)
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for j in range(num_dacs)]
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@portable
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def get_num_boards(self):
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return self.num_boards
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@portable
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def get_num_channels(self):
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return self.num_channels
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@portable
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def get_num_frames(self):
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return self.num_frames
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def get_freq(self):
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return self.freq
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def set_freq(self, freq):
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self.freq = float(freq)
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@portable
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def set_reg(self, adr, data, board):
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raise NotImplementedError
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@portable
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def get_reg(self, adr, board):
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raise NotImplementedError
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@portable
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def write_mem(self, mem, adr, data, board=0xf):
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raise NotImplementedError
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@portable
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def read_mem(self, mem, adr, data, board=0xf, buffer=8):
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raise NotImplementedError
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@portable
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def set_config(self, reset=0, clk2x=0, enable=1,
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trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
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"""Set the configuration register.
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Args:
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reset (bool): Reset the board. Memory is not reset. Self-clearing.
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clk2x (bool): Enable the clock multiplier (100 MHz instead of 50
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MHz)
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enable (bool): Enable the reading and execution of waveform data
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from memory.
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trigger (bool): Soft trigger. Logical or with the ``F1 TTL Input``
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hardware trigger.
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aux_miso (bool): Drive SPI MISO on the AUX/``F5 OUT`` TTL port of
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each board. If ``False``/``0``, drive the masked logical OR of
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the DAC channels' aux data.
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aux_dac (int): DAC channel mask for AUX/F5. Each bit represents
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one channel. AUX/F5 is: ``aux_miso ? spi_miso :
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(aux_dac & Cat(_.aux for _ in channels) != 0)``
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board (int): Board to write to (0-0xe), 0xf for all boards.
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"""
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config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
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(trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
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self.set_reg(PDQ_ADR_CONFIG, config, board)
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@portable
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def get_config(self, board=0xf):
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"""Read configuration register.
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.. seealso: :meth:`set_config`
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"""
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return self.get_reg(PDQ_ADR_CONFIG, board)
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@portable
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def set_crc(self, crc=0, board=0xf):
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"""Set/reset the checksum register.
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Args:
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crc (int): Checksum value to write.
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board (int): Board to write to (0-0xe), 0xf for all boards.
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"""
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self.set_reg(PDQ_ADR_CRC, crc, board)
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@portable
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def get_crc(self, board=0xf):
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"""Read checksum register.
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.. seealso:: :meth:`set_crc`
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"""
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return self.get_reg(PDQ_ADR_CRC, board)
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@portable
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def set_frame(self, frame, board=0xf):
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"""Set the current frame.
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Args:
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frame (int): Frame to select.
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board (int): Board to write to (0-0xe), 0xf for all boards.
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"""
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self.set_reg(PDQ_ADR_FRAME, frame, board)
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@portable
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def get_frame(self, board=0xf):
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"""Read frame selection register.
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.. seealso:: :meth:`set_frame`
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"""
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return self.get_reg(PDQ_ADR_FRAME, board)
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def program_segments(self, segments, data):
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"""Append the wavesynth lines to the given segments.
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Args:
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segments (list[Segment]): List of :class:`Segment` to append the
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lines to.
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data (list): List of wavesynth lines.
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"""
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for i, line in enumerate(data):
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dac_divider = line.get("dac_divider", 1)
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shift = int(log(dac_divider, 2))
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if 2**shift != dac_divider:
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raise ValueError("only power-of-two dac_dividers supported")
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duration = line["duration"]
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trigger = line.get("trigger", False)
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for segment, data in zip(segments, line["channel_data"]):
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silence = data.pop("silence", False)
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if len(data) != 1:
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raise ValueError("only one target per channel and line "
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"supported")
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for target, target_data in data.items():
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getattr(segment, target)(
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shift=shift, duration=duration, trigger=trigger,
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silence=silence, **target_data)
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def program(self, program, channels=None):
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"""Serialize a wavesynth program and write it to the channels
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in the stack.
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The :class:`Channel` targeted are cleared and each frame in the
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wavesynth program is appended to a fresh set of :class:`Segment`
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of the channels. All segments are allocated, the frame address tale
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is generated, the channels are serialized and their memories are
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written.
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Short single-cycle lines are prepended and appended to each frame to
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allow proper write interlocking and to assure that the memory reader
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can be reliably parked in the frame address table.
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The first line of each frame is mandatorily triggered.
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Args:
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program (list): Wavesynth program to serialize.
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channels (list[int]): Channel indices to use. If unspecified, all
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channels are used.
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"""
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if channels is None:
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channels = range(self.num_channels)
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chs = [self.channels[i] for i in channels]
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for channel in chs:
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channel.clear()
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for frame in program:
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segments = [c.new_segment() for c in chs]
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self.program_segments(segments, frame)
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# append an empty line to stall the memory reader before jumping
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# through the frame table (`wait` does not prevent reading
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# the next line)
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for segment in segments:
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segment.line(typ=3, data=b"", trigger=True, duration=1, aux=1,
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jump=True)
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for channel, ch in zip(channels, chs):
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self.write_mem(channel, ch.serialize())
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def ping(self):
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"""Ping method returning True. Required for ARTIQ remote
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controller."""
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return True
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