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artiq/soc/targets
2015-07-29 11:45:15 -06:00
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artiq_kc705.py kc705: generate 10MHz clock on GPIO SMA 2015-07-28 18:56:47 +08:00
artiq_pipistrello.py pipistrello: drop bitgen_opt change (done upstream) 2015-07-29 11:45:15 -06:00