mirror of https://github.com/m-labs/artiq.git
54 lines
1.8 KiB
Python
54 lines
1.8 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bus import wishbone
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from misoclib.cpu import mor1kx
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from misoclib.mem.sdram.frontend.wishbone2lasmi import WB2LASMI
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from misoclib.soc import mem_decoder
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class KernelCPU(Module):
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def __init__(self, platform, lasmim,
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exec_address=0x40020000,
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main_mem_origin=0x40000000,
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l2_size=8192):
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self._reset = CSRStorage(reset=1)
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# # #
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self._wb_slaves = []
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# CPU core
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self.clock_domains.cd_sys_kernel = ClockDomain()
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self.comb += [
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self.cd_sys_kernel.clk.eq(ClockSignal()),
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self.cd_sys_kernel.rst.eq(self._reset.storage)
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]
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self.submodules.cpu = RenameClockDomains(
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mor1kx.MOR1KX(platform, exec_address),
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"sys_kernel")
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# DRAM access
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# XXX Vivado 2014.X workaround
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.wishbone2lasmi = FullMemoryWE(
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WB2LASMI(l2_size//4, lasmim))
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else:
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self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
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self.add_wb_slave(mem_decoder(main_mem_origin),
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self.wishbone2lasmi.wishbone)
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def get_csrs(self):
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return [self._reset]
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def do_finalize(self):
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self.submodules.wishbonecon = wishbone.InterconnectShared(
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[self.cpu.ibus, self.cpu.dbus], self._wb_slaves, register=True)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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