mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-19 00:16:29 +08:00
139 lines
5.2 KiB
Python
139 lines
5.2 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.cpu.peripherals import gpio
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from targets.pipistrello import BaseSoC
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from artiq.gateware import rtio, ad9858
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_tester_io = [
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("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")),
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
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("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
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("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
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("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
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("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
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("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
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("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
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("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
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("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
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("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
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("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
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("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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class _RTIOMiniCRG(Module, AutoCSR):
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def __init__(self, platform):
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self._r_clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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# 80MHz -> 125MHz
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rtio_internal_clk = Signal()
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self.specials += Instance("DCM_CLKGEN",
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p_CLKFXDV_DIVIDE=2,
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p_CLKFX_DIVIDE=16,
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p_CLKFX_MD_MAX=1.6,
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p_CLKFX_MULTIPLY=25,
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p_CLKIN_PERIOD=12.5,
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p_SPREAD_SPECTRUM="NONE",
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p_STARTUP_WAIT="FALSE",
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i_CLKIN=ClockSignal(),
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o_CLKFX=rtio_internal_clk,
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i_FREEZEDCM=0,
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i_RST=ResetSignal())
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rtio_external_clk = platform.request("dds_clock")
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platform.add_period_constraint(rtio_external_clk, 8.0)
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._r_clock_sel.storage,
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o_O=self.cd_rtio.clk)
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platform.add_platform_command("""
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NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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""", rtio_clk=rtio_internal_clk)
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class ARTIQMidiSoC(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1),
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platform.request("user_led", 2),
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platform.request("user_led", 3),
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platform.request("user_led", 4),
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platform.request("ext_led", 0),
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))
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fud = Signal()
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt", i) for i in range(2)]
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rtio_ins += [platform.request("xtrig", 0)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
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rtio_outs += [fud]
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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rtio_ins + rtio_outs,
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output_only_pads=set(rtio_outs))
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self.submodules.rtio = rtio.RTIO(self.rtiophy,
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clk_freq=125000000,
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ififo_depth=512)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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self.comb += dds_pads.fud_n.eq(~fud)
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default_subtarget = ARTIQMidiSoC
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