mirror of https://github.com/m-labs/artiq.git
590 lines
20 KiB
Rust
590 lines
20 KiB
Rust
pub mod jesd {
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use board_misoc::{csr, clock};
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pub fn reset(reset: bool) {
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unsafe {
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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}
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}
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pub fn enable(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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}
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pub fn phy_done(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_phy_done_read)() != 0
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}
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}
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pub fn ready(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
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}
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}
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pub fn prbs(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
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}
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clock::spin_us(5000);
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}
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pub fn stpl(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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pub fn jsync(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
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}
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}
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}
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pub mod jdac {
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use board_misoc::{csr, clock};
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use board_artiq::drtioaux;
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use super::jesd;
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use super::super::jdac_common;
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pub fn basic_request(dacno: u8, reqno: u8, param: u8) -> Result<u8, &'static str> {
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
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destination: 0,
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dacno: dacno,
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reqno: reqno,
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param: param
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}) {
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error!("aux packet error ({})", e);
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return Err("aux packet error while sending for JESD DAC basic request");
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}
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match drtioaux::recv_timeout(1, Some(1000)) {
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Ok(drtioaux::Packet::JdacBasicReply { succeeded, retval }) => {
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if succeeded {
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Ok(retval)
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} else {
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error!("JESD DAC basic request failed (dacno={}, reqno={})", dacno, reqno);
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Err("remote error status to JESD DAC basic request")
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}
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},
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Ok(packet) => {
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error!("received unexpected aux packet: {:?}", packet);
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Err("unexpected aux packet in reply to JESD DAC basic request")
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},
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Err(e) => {
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error!("aux packet error ({})", e);
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Err("aux packet error while waiting for JESD DAC basic reply")
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}
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}
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}
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pub fn init() -> Result<(), &'static str> {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("DAC-{} initializing...", dacno);
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jesd::enable(dacno, true);
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clock::spin_us(10_000);
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if !jesd::phy_done(dacno) {
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error!("JESD core PHY not done");
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return Err("JESD core PHY not done");
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}
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basic_request(dacno, jdac_common::INIT, 0)?;
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// JESD ready depends on JSYNC being valid, so DAC init needs to happen first
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if !jesd::ready(dacno) {
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error!("JESD core reported not ready, sending DAC status print request");
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basic_request(dacno, jdac_common::PRINT_STATUS, 0)?;
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return Err("JESD core reported not ready");
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}
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jesd::prbs(dacno, true);
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basic_request(dacno, jdac_common::PRBS, 0)?;
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jesd::prbs(dacno, false);
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basic_request(dacno, jdac_common::INIT, 0)?;
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clock::spin_us(5000);
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if !jesd::jsync(dacno) {
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error!("JESD core reported bad SYNC");
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return Err("JESD core reported bad SYNC");
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}
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info!(" ...done initializing");
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}
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Ok(())
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}
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pub fn stpl() -> Result<(), &'static str> {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("Running STPL test on DAC-{}...", dacno);
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jesd::stpl(dacno, true);
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basic_request(dacno, jdac_common::STPL, 0)?;
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jesd::stpl(dacno, false);
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info!(" ...done STPL test");
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}
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Ok(())
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}
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}
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pub mod jesd204sync {
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use board_misoc::{csr, clock, config};
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use super::jdac;
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use super::super::jdac_common;
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const HMC7043_ANALOG_DELAY_RANGE: u8 = 24;
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const FPGA_CLK_DIV: u16 = 16; // Keep in sync with hmc830_7043.rs
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const SYSREF_DIV: u16 = 256; // Keep in sync with hmc830_7043.rs
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fn hmc7043_sysref_delay_dac(dacno: u8, phase_offset: u8) -> Result<(), &'static str> {
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match jdac::basic_request(dacno, jdac_common::SYSREF_DELAY_DAC, phase_offset) {
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Ok(_) => Ok(()),
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Err(e) => Err(e)
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}
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}
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fn hmc7043_sysref_slip() -> Result<(), &'static str> {
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match jdac::basic_request(0, jdac_common::SYSREF_SLIP, 0) {
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Ok(_) => Ok(()),
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Err(e) => Err(e)
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}
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}
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fn ad9154_sync(dacno: u8) -> Result<bool, &'static str> {
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match jdac::basic_request(dacno, jdac_common::SYNC, 0) {
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Ok(0) => Ok(false),
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Ok(_) => Ok(true),
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Err(e) => Err(e)
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}
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}
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fn measure_ddmdt_phase_raw() -> Result<i32, &'static str> {
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Ok(jdac::basic_request(0, jdac_common::DDMTD_SYSREF_RAW, 0)? as i32)
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}
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fn measure_ddmdt_phase() -> Result<i32, &'static str> {
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Ok(jdac::basic_request(0, jdac_common::DDMTD_SYSREF, 0)? as i32)
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}
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fn test_ddmtd_stability(raw: bool, tolerance: i32) -> Result<(), &'static str> {
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info!("testing DDMTD stability (raw={}, tolerance={})...", raw, tolerance);
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let modulo = if raw { jdac_common::RAW_DDMTD_N } else { jdac_common::DDMTD_N };
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let measurement = if raw { measure_ddmdt_phase_raw } else { measure_ddmdt_phase };
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let ntests = if raw { 150 } else { 15 };
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let mut max_pkpk = 0;
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for _ in 0..32 {
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// If we are near the edges, wraparound can throw off the simple min/max computation.
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// In this case, add an offset to get near the center.
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let quadrant = measure_ddmdt_phase()?;
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let center_offset =
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if quadrant < jdac_common::DDMTD_N/4 || quadrant > 3*jdac_common::DDMTD_N/4 {
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modulo/2
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} else {
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0
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};
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let mut min = modulo;
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let mut max = 0;
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for _ in 0..ntests {
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let m = (measurement()? + center_offset) % modulo;
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if m < min {
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min = m;
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}
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if m > max {
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max = m;
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}
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}
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let pkpk = max - min;
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if pkpk > max_pkpk {
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max_pkpk = pkpk;
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}
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if pkpk > tolerance {
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error!(" ...excessive peak-peak jitter: {} (min={} max={} center_offset={})", pkpk,
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min, max, center_offset);
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return Err("excessive DDMTD peak-peak jitter");
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}
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hmc7043_sysref_slip();
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}
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info!(" ...passed, peak-peak jitter: {}", max_pkpk);
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Ok(())
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}
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fn test_slip_ddmtd() -> Result<(), &'static str> {
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// expected_step = (RTIO clock frequency)*(DDMTD N)/(HMC7043 CLKIN frequency)
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let expected_step = 8;
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let tolerance = 1;
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info!("testing HMC7043 SYSREF slip against DDMTD...");
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let mut old_phase = measure_ddmdt_phase()?;
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for _ in 0..1024 {
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hmc7043_sysref_slip();
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let phase = measure_ddmdt_phase()?;
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let step = (jdac_common::DDMTD_N + old_phase - phase) % jdac_common::DDMTD_N;
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if (step - expected_step).abs() > tolerance {
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error!(" ...got unexpected step: {} ({} -> {})", step, old_phase, phase);
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return Err("HMC7043 SYSREF slip produced unexpected DDMTD step");
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}
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old_phase = phase;
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}
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info!(" ...passed");
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Ok(())
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}
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fn sysref_sh_error() -> bool {
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unsafe {
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csr::sysref_sampler::sh_error_reset_write(1);
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clock::spin_us(1);
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csr::sysref_sampler::sh_error_reset_write(0);
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clock::spin_us(10);
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csr::sysref_sampler::sh_error_read() != 0
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}
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}
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const SYSREF_SH_PRECISION_SHIFT: i32 = 5;
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const SYSREF_SH_PRECISION: i32 = 1 << SYSREF_SH_PRECISION_SHIFT;
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const SYSREF_SH_MOD: i32 = 1 << (jdac_common::DDMTD_N_SHIFT + SYSREF_SH_PRECISION_SHIFT);
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#[derive(Default)]
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struct SysrefShLimits {
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rising_phases: [i32; SYSREF_SH_PRECISION as usize],
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falling_phases: [i32; SYSREF_SH_PRECISION as usize],
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}
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fn measure_sysref_sh_limits() -> Result<SysrefShLimits, &'static str> {
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let mut ret = SysrefShLimits::default();
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let mut nslips = 0;
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let mut rising_n = 0;
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let mut falling_n = 0;
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let mut previous = sysref_sh_error();
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while rising_n < SYSREF_SH_PRECISION || falling_n < SYSREF_SH_PRECISION {
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hmc7043_sysref_slip();
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nslips += 1;
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if nslips > 1024 {
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return Err("too many slips and not enough SYSREF S/H error transitions");
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}
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let current = sysref_sh_error();
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let phase = measure_ddmdt_phase()?;
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if current && !previous && rising_n < SYSREF_SH_PRECISION {
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ret.rising_phases[rising_n as usize] = phase << SYSREF_SH_PRECISION_SHIFT;
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rising_n += 1;
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}
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if !current && previous && falling_n < SYSREF_SH_PRECISION {
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ret.falling_phases[falling_n as usize] = phase << SYSREF_SH_PRECISION_SHIFT;
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falling_n += 1;
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}
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previous = current;
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}
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Ok(ret)
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}
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fn max_phase_deviation(average: i32, phases: &[i32]) -> i32 {
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let mut ret = 0;
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for phase in phases.iter() {
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let deviation = (phase - average + jdac_common::DDMTD_N) % jdac_common::DDMTD_N;
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if deviation > ret {
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ret = deviation;
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}
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}
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return ret;
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}
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fn reach_sysref_ddmtd_target(target: i32, tolerance: i32) -> Result<i32, &'static str> {
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for _ in 0..1024 {
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let delta = (measure_ddmdt_phase()? - target + jdac_common::DDMTD_N) % jdac_common::DDMTD_N;
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if delta <= tolerance {
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return Ok(delta)
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}
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hmc7043_sysref_slip();
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}
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Err("failed to reach SYSREF DDMTD phase target")
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}
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fn calibrate_sysref_target(rising_average: i32, falling_average: i32) -> Result<i32, &'static str> {
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info!("calibrating SYSREF DDMTD target phase...");
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let coarse_target =
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if rising_average < falling_average {
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(rising_average + falling_average)/2
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} else {
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((falling_average - (jdac_common::DDMTD_N - rising_average))/2 + jdac_common::DDMTD_N) % jdac_common::DDMTD_N
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};
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info!(" SYSREF calibration coarse target: {}", coarse_target);
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reach_sysref_ddmtd_target(coarse_target, 8)?;
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let target = measure_ddmdt_phase()?;
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info!(" ...done, target={}", target);
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Ok(target)
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}
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fn sysref_get_tsc_phase_raw() -> Result<u8, &'static str> {
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if sysref_sh_error() {
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return Err("SYSREF failed S/H timing");
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}
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let ret = unsafe { csr::sysref_sampler::sysref_phase_read() };
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Ok(ret)
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}
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// Note: the code below assumes RTIO/SYSREF frequency ratio is a power of 2
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fn sysref_get_tsc_phase() -> Result<i32, &'static str> {
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let mask = (SYSREF_DIV/FPGA_CLK_DIV - 1) as u8;
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Ok((sysref_get_tsc_phase_raw()? & mask) as i32)
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}
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pub fn test_sysref_frequency() -> Result<(), &'static str> {
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info!("testing SYSREF frequency against raw TSC phase bit toggles...");
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let mut all_toggles = 0;
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let initial_phase = sysref_get_tsc_phase_raw()?;
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for _ in 0..20000 {
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clock::spin_us(1);
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all_toggles |= sysref_get_tsc_phase_raw()? ^ initial_phase;
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}
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let ratio = (SYSREF_DIV/FPGA_CLK_DIV) as u8;
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let expected_toggles = 0xff ^ (ratio - 1);
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if all_toggles == expected_toggles {
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info!(" ...done (0x{:02x})", all_toggles);
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Ok(())
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} else {
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error!(" ...unexpected toggles: got 0x{:02x}, expected 0x{:02x}",
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all_toggles, expected_toggles);
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Err("unexpected toggles")
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}
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}
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fn sysref_slip_rtio_cycle() {
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for _ in 0..FPGA_CLK_DIV {
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hmc7043_sysref_slip();
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}
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}
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pub fn test_slip_tsc() -> Result<(), &'static str> {
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info!("testing HMC7043 SYSREF slip against TSC phase...");
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let initial_phase = sysref_get_tsc_phase()?;
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let modulo = (SYSREF_DIV/FPGA_CLK_DIV) as i32;
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for i in 0..128 {
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sysref_slip_rtio_cycle();
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let expected_phase = (initial_phase + i + 1) % modulo;
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let phase = sysref_get_tsc_phase()?;
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if phase != expected_phase {
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error!(" ...unexpected TSC phase: got {}, expected {} ", phase, expected_phase);
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return Err("HMC7043 SYSREF slip produced unexpected TSC phase");
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}
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}
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info!(" ...done");
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Ok(())
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}
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pub fn sysref_rtio_align() -> Result<(), &'static str> {
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info!("aligning SYSREF with RTIO TSC...");
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let mut nslips = 0;
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loop {
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sysref_slip_rtio_cycle();
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if sysref_get_tsc_phase()? == 0 {
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info!(" ...done");
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return Ok(())
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}
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nslips += 1;
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if nslips > SYSREF_DIV/FPGA_CLK_DIV {
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return Err("failed to find SYSREF transition aligned with RTIO TSC");
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}
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}
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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test_ddmtd_stability(true, 4)?;
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test_ddmtd_stability(false, 1)?;
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test_slip_ddmtd()?;
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info!("determining SYSREF S/H limits...");
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let sysref_sh_limits = measure_sysref_sh_limits()?;
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let rising_average = jdac_common::average_phases(&sysref_sh_limits.rising_phases, SYSREF_SH_MOD);
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let falling_average = jdac_common::average_phases(&sysref_sh_limits.falling_phases, SYSREF_SH_MOD);
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let rising_max_deviation = max_phase_deviation(rising_average, &sysref_sh_limits.rising_phases);
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let falling_max_deviation = max_phase_deviation(falling_average, &sysref_sh_limits.falling_phases);
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let rising_average = rising_average >> SYSREF_SH_PRECISION_SHIFT;
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let falling_average = falling_average >> SYSREF_SH_PRECISION_SHIFT;
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let rising_max_deviation = rising_max_deviation >> SYSREF_SH_PRECISION_SHIFT;
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let falling_max_deviation = falling_max_deviation >> SYSREF_SH_PRECISION_SHIFT;
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info!(" SYSREF S/H average limits (DDMTD phases): {} {}", rising_average, falling_average);
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info!(" SYSREF S/H maximum limit deviation: {} {}", rising_max_deviation, falling_max_deviation);
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if rising_max_deviation > 8 || falling_max_deviation > 8 {
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return Err("excessive SYSREF S/H limit deviation");
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}
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info!(" ...done");
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let entry = config::read_str("sysref_ddmtd_phase_fpga", |r| r.map(|s| s.parse()));
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let target_phase = match entry {
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Ok(Ok(phase)) => {
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info!("using FPGA SYSREF DDMTD phase target from config: {}", phase);
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phase
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}
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_ => {
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let phase = calibrate_sysref_target(rising_average, falling_average)?;
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if let Err(e) = config::write_int("sysref_ddmtd_phase_fpga", phase as u32) {
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error!("failed to update FPGA SYSREF DDMTD phase target in config: {}", e);
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}
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phase
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}
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};
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info!("aligning SYSREF with RTIO clock...");
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let delta = reach_sysref_ddmtd_target(target_phase, 3)?;
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if sysref_sh_error() {
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return Err("SYSREF does not meet S/H timing at DDMTD phase target");
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}
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info!(" ...done, delta={}", delta);
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test_sysref_frequency()?;
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test_slip_tsc()?;
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sysref_rtio_align()?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn sysref_cal_dac(dacno: u8) -> Result<u8, &'static str> {
|
|
info!("calibrating SYSREF delay at DAC-{}...", dacno);
|
|
|
|
// Allocate for more than expected as jitter may create spurious entries.
|
|
let mut limits_buf = [0; 8];
|
|
let mut n_limits = 0;
|
|
|
|
limits_buf[n_limits] = -1;
|
|
n_limits += 1;
|
|
|
|
// avoid spurious rotation at delay=0
|
|
hmc7043_sysref_delay_dac(dacno, 0);
|
|
ad9154_sync(dacno)?;
|
|
|
|
for scan_delay in 0..HMC7043_ANALOG_DELAY_RANGE {
|
|
hmc7043_sysref_delay_dac(dacno, scan_delay);
|
|
if ad9154_sync(dacno)? {
|
|
limits_buf[n_limits] = scan_delay as i16;
|
|
n_limits += 1;
|
|
if n_limits >= limits_buf.len() - 1 {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
limits_buf[n_limits] = HMC7043_ANALOG_DELAY_RANGE as i16;
|
|
n_limits += 1;
|
|
|
|
info!(" using limits: {:?}", &limits_buf[..n_limits]);
|
|
|
|
let mut delay = 0;
|
|
let mut best_margin = 0;
|
|
|
|
for i in 0..(n_limits-1) {
|
|
let margin = limits_buf[i+1] - limits_buf[i];
|
|
if margin > best_margin {
|
|
best_margin = margin;
|
|
delay = ((limits_buf[i+1] + limits_buf[i])/2) as u8;
|
|
}
|
|
}
|
|
|
|
info!(" ...done, delay={}", delay);
|
|
Ok(delay)
|
|
}
|
|
|
|
fn sysref_dac_align(dacno: u8, delay: u8) -> Result<(), &'static str> {
|
|
let tolerance = 5;
|
|
|
|
info!("verifying SYSREF margins at DAC-{}...", dacno);
|
|
|
|
// avoid spurious rotation at delay=0
|
|
hmc7043_sysref_delay_dac(dacno, 0);
|
|
ad9154_sync(dacno)?;
|
|
|
|
let mut rotation_seen = false;
|
|
for scan_delay in 0..HMC7043_ANALOG_DELAY_RANGE {
|
|
hmc7043_sysref_delay_dac(dacno, scan_delay);
|
|
if ad9154_sync(dacno)? {
|
|
rotation_seen = true;
|
|
let distance = (scan_delay as i16 - delay as i16).abs();
|
|
if distance < tolerance {
|
|
error!(" rotation at delay={} is {} delay steps from target (FAIL)", scan_delay, distance);
|
|
return Err("insufficient SYSREF margin at DAC");
|
|
} else {
|
|
info!(" rotation at delay={} is {} delay steps from target (PASS)", scan_delay, distance);
|
|
}
|
|
}
|
|
}
|
|
|
|
if !rotation_seen {
|
|
return Err("no rotation seen when scanning DAC SYSREF delay");
|
|
}
|
|
|
|
info!(" ...done");
|
|
|
|
// We tested that the value is correct - now use it
|
|
info!("synchronizing DAC-{}", dacno);
|
|
hmc7043_sysref_delay_dac(dacno, delay);
|
|
ad9154_sync(dacno)?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub fn sysref_auto_dac_align() -> Result<(), &'static str> {
|
|
// We assume that DAC SYSREF traces are length-matched so only one delay
|
|
// value is needed, and we use DAC-0 as calibration reference.
|
|
|
|
let entry = config::read_str("sysref_7043_delay_dac", |r| r.map(|s| s.parse()));
|
|
let delay = match entry {
|
|
Ok(Ok(delay)) => {
|
|
info!("using DAC SYSREF delay from config: {}", delay);
|
|
delay
|
|
},
|
|
_ => {
|
|
let delay = sysref_cal_dac(0)?;
|
|
if let Err(e) = config::write_int("sysref_7043_delay_dac", delay as u32) {
|
|
error!("failed to update DAC SYSREF delay in config: {}", e);
|
|
}
|
|
delay
|
|
}
|
|
};
|
|
|
|
for dacno in 0..csr::JDCG.len() {
|
|
sysref_dac_align(dacno as u8, delay)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
pub fn sysref_auto_align() {
|
|
if let Err(e) = sysref_auto_rtio_align() {
|
|
error!("failed to align SYSREF at FPGA: {}", e);
|
|
}
|
|
if let Err(e) = sysref_auto_dac_align() {
|
|
error!("failed to align SYSREF at DAC: {}", e);
|
|
}
|
|
}
|
|
|
|
pub fn resync_dacs() -> Result<(), &'static str> {
|
|
for dacno in 0..csr::JDCG.len() {
|
|
info!("resynchronizing DAC-{}", dacno);
|
|
ad9154_sync(dacno as u8)?;
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|