mirror of https://github.com/m-labs/artiq
78 lines
2.6 KiB
Python
78 lines
2.6 KiB
Python
from .spr import mtspr, mfspr
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from artiq.language.core import kernel
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_MAX_SPRS_PER_GRP_BITS = 11
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_SPRGROUP_PC = 7 << _MAX_SPRS_PER_GRP_BITS
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_SPR_PCMR_CP = 0x00000001 # Counter present
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_SPR_PCMR_CISM = 0x00000004 # Count in supervisor mode
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_SPR_PCMR_CIUM = 0x00000008 # Count in user mode
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_SPR_PCMR_LA = 0x00000010 # Load access event
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_SPR_PCMR_SA = 0x00000020 # Store access event
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_SPR_PCMR_IF = 0x00000040 # Instruction fetch event
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_SPR_PCMR_DCM = 0x00000080 # Data cache miss event
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_SPR_PCMR_ICM = 0x00000100 # Insn cache miss event
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_SPR_PCMR_IFS = 0x00000200 # Insn fetch stall event
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_SPR_PCMR_LSUS = 0x00000400 # LSU stall event
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_SPR_PCMR_BS = 0x00000800 # Branch stall event
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_SPR_PCMR_DTLBM = 0x00001000 # DTLB miss event
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_SPR_PCMR_ITLBM = 0x00002000 # ITLB miss event
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_SPR_PCMR_DDS = 0x00004000 # Data dependency stall event
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_SPR_PCMR_WPE = 0x03ff8000 # Watchpoint events
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@kernel(flags={"nowrite", "nounwind"})
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def _PCCR(n):
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return _SPRGROUP_PC + n
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@kernel(flags={"nowrite", "nounwind"})
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def _PCMR(n):
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return _SPRGROUP_PC + 8 + n
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class CorePCU:
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"""Core device performance counter unit (PCU) access"""
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def __init__(self, dmgr, core_device="core"):
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self.core = dmgr.get(core_device)
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@kernel
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def start(self):
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"""
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Configure and clear the kernel CPU performance counters.
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The eight counters are configured to count the following events:
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* Load or store
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* Instruction fetch
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* Data cache miss
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* Instruction cache miss
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* Instruction fetch stall
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* Load-store-unit stall
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* Branch stall
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* Data dependency stall
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"""
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for i in range(8):
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if not mfspr(_PCMR(i)) & _SPR_PCMR_CP:
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raise ValueError("counter not present")
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mtspr(_PCMR(i), 0)
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mtspr(_PCCR(i), 0)
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mtspr(_PCMR(0), _SPR_PCMR_CISM | _SPR_PCMR_LA | _SPR_PCMR_SA)
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mtspr(_PCMR(1), _SPR_PCMR_CISM | _SPR_PCMR_IF)
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mtspr(_PCMR(2), _SPR_PCMR_CISM | _SPR_PCMR_DCM)
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mtspr(_PCMR(3), _SPR_PCMR_CISM | _SPR_PCMR_ICM)
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mtspr(_PCMR(4), _SPR_PCMR_CISM | _SPR_PCMR_IFS)
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mtspr(_PCMR(5), _SPR_PCMR_CISM | _SPR_PCMR_LSUS)
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mtspr(_PCMR(6), _SPR_PCMR_CISM | _SPR_PCMR_BS)
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mtspr(_PCMR(7), _SPR_PCMR_CISM | _SPR_PCMR_DDS)
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@kernel
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def get(self, r):
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"""
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Read the performance counters and store the counts in the
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array provided.
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:param list[int] r: array to store the counter values
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"""
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for i in range(8):
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r[i] = mfspr(_PCCR(i))
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