mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-13 13:46:36 +08:00
Sebastien Bourdeauducq
657afd770e
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
50 lines
1.3 KiB
Python
50 lines
1.3 KiB
Python
def set_dict(e, **k):
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for k, v in k.items():
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if isinstance(v, dict):
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yield from set_dict(getattr(e, k), **v)
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else:
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yield getattr(e, k).eq(v)
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def xfer(dut, **kw):
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ep = []
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for e, v in kw.items():
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e = getattr(dut, e)
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yield from set_dict(e, **v)
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ep.append(e)
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for e in ep:
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yield e.stb.eq(1)
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while ep:
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yield
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for e in ep[:]:
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if hasattr(e, "busy") and (yield e.busy):
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raise ValueError(e, "busy")
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if not hasattr(e, "ack") or (yield e.ack):
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yield e.stb.eq(0)
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ep.remove(e)
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def szip(*iters):
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active = {it: None for it in iters}
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while active:
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for it in list(active):
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while True:
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try:
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val = it.send(active[it])
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except StopIteration:
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del active[it]
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break
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if val is None:
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break
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else:
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active[it] = (yield val)
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val = (yield None)
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for it in active:
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active[it] = val
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def rtio_xfer(dut, **kwargs):
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yield from szip(*(
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xfer(dut.phys_named[k].rtlink, o={"data": v})
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for k, v in kwargs.items()))
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