mirror of https://github.com/m-labs/artiq.git
129 lines
3.6 KiB
Python
129 lines
3.6 KiB
Python
import unittest
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import random
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from migen import *
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from artiq.gateware.serwb import scrambler
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from artiq.gateware.serwb import SERWBCore
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from misoc.interconnect.wishbone import SRAM
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class FakeInit(Module):
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def __init__(self):
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self.ready = 1
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class FakeSerdes(Module):
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def __init__(self):
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self.tx_k = Signal(4)
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self.tx_d = Signal(32)
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self.rx_k = Signal(4)
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self.rx_d = Signal(32)
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class FakePHY(Module):
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cd = "sys"
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def __init__(self):
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self.init = FakeInit()
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self.serdes = FakeSerdes()
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class DUTScrambler(Module):
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def __init__(self):
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self.submodules.scrambler = scrambler.Scrambler(sync_interval=16)
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self.submodules.descrambler = scrambler.Descrambler()
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self.comb += [
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self.scrambler.source.connect(self.descrambler.sink),
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self.descrambler.source.ready.eq(1)
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]
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class DUTCore(Module):
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def __init__(self, **kwargs):
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# wishbone slave
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phy_slave = FakePHY()
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serwb_slave = SERWBCore(phy_slave, int(1e6), "slave", **kwargs)
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self.submodules += phy_slave, serwb_slave
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# wishbone master
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phy_master = FakePHY()
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serwb_master = SERWBCore(phy_master, int(1e6), "master", **kwargs)
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self.submodules += phy_master, serwb_master
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# connect phy
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self.comb += [
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phy_master.serdes.rx_k.eq(phy_slave.serdes.tx_k),
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phy_master.serdes.rx_d.eq(phy_slave.serdes.tx_d),
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phy_slave.serdes.rx_k.eq(phy_master.serdes.tx_k),
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phy_slave.serdes.rx_d.eq(phy_master.serdes.tx_d)
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]
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# add wishbone sram to wishbone master
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sram = SRAM(1024, bus=serwb_master.etherbone.wishbone.bus)
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self.submodules += sram
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# expose wishbone slave
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self.wishbone = serwb_slave.etherbone.wishbone.bus
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class TestSERWBCore(unittest.TestCase):
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def test_scrambler(self):
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def generator(dut):
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i = 0
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last_data = -1
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while i != 256:
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# stim
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if (yield dut.scrambler.sink.ready):
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i += 1
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yield dut.scrambler.sink.data.eq(i)
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# check
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if (yield dut.descrambler.source.valid):
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current_data = (yield dut.descrambler.source.data)
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if (current_data != (last_data + 1)):
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dut.errors += 1
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last_data = current_data
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# cycle
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yield
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dut = DUTScrambler()
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dut.errors = 0
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run_simulation(dut, generator(dut))
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self.assertEqual(dut.errors, 0)
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def test_serwb(self):
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def generator(dut):
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# prepare test
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prng = random.Random(42)
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data_base = 0x100
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data_length = 4
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datas_w = [prng.randrange(2**32) for i in range(data_length)]
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datas_r = []
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# write
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for i in range(data_length):
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yield from dut.wishbone.write(data_base + i, datas_w[i])
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# read
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for i in range(data_length):
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datas_r.append((yield from dut.wishbone.read(data_base + i)))
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# check
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for i in range(data_length):
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if datas_r[i] != datas_w[i]:
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dut.errors += 1
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# scrambling off
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dut = DUTCore(with_scrambling=False)
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dut.errors = 0
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run_simulation(dut, generator(dut))
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self.assertEqual(dut.errors, 0)
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# scrambling on
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dut = DUTCore(with_scrambling=True)
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dut.errors = 0
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run_simulation(dut, generator(dut))
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self.assertEqual(dut.errors, 0)
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