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mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
artiq/soc
2015-06-18 12:18:45 +02:00
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runtime runtime/mailbox: remove flush of L2 cache (L2 cache is now shared between CPUs) 2015-06-18 12:18:45 +02:00
targets gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache 2015-06-18 12:18:03 +02:00